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參數(shù)資料
| 型號： | CR16MPS544V9Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 105K |
| 代理商： | CR16MPS544V9Y |
5
C
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI in-
put pin.
3.6
MULTI-INPUT WAKE-UP
The Multi-Input Wake-Up (MIWU16) module can be used for
either of two purposes: to provide inputs for waking up (exit-
ing) from the HALT, IDLE, or Power Save mode; or to provide
general-purpose edge-triggered maskable interrupts from
external sources. This 16-channel module generates four
programmable interrupts to the CPU based on the signals re-
ceived on its 16 input channels. Channels can be individually
enabled or disabled, and programmed to respond to positive
or negative edges.
3.7
DUAL CLOCK AND RESET
The Dual Clock and Reset (CLK2RES) module generates a
high-speed main system clock from an external crystal net-
work. It also provides the main system reset signal and a
power-on reset function.
This module also generates a slow system clock (32.768
kHz) from another external crystal network. The slow clock is
used for operating the device in power-save mode. Without
a 32.768kHz external crystal network, the low speed system
clock can be derived from the high speed clock by a prescal-
er.
Also, two independent clocks divided down from the high
speed clock are available on output pins.
3.8
POWER MANAGEMENT
The Power Management Module (PMM) improves the effi-
ciency of the CR16MBR5 device by changing the operating
mode and therefore the power consumption according to the
required level of activity.
The CR16MBR5 device can operate in any of four power
modes:
— Active: The device operates at full speed using the
high-frequency clock. All device functions are fully op-
erational.
— Power Save: The device operates at reduced speed
using the slow clock. The CPU and some modules can
continue to operate at this low speed.
— IDLE: The device is inactive except for the Power Man-
agement Module and Timing and Watchdog Module,
which continue to operate using the slow clock.
— HALT: The device is inactive but still retains its internal
state (RAM and register contents).
3.9
MULTI-FUNCTION TIMER
The Multi-Function Timer (MFT16) module contains two inde-
pendent timer/counter units called MFT1 and MFT2, each
containing a pair of 16-bit timer/counter registers. Each timer/
counter unit can be configured to operate in any of the follow-
ing modes:
— Processor-Independent
(PWM) mode, which generates pulses of a specified
width and duty cycle, and which also provides a gener-
al-purpose timer/counter.
— Dual Input Capture mode, which measures the
elapsed time between occurrences of external events,
Pulse
Width
Modulation
and which also provides a general-purpose timer/
counter.
— Dual Independent Timer mode, which generates sys-
tem timing signals or counts occurrences of external
events.
— Single Input Capture and Single Timer mode, which
provides one external event counter and one system
timer.
3.10
VERSATILE TIMER UNIT
The Versatile Timer Unit (VTU) module contains four inde-
pendent timer subsystems, each operating in either dual 8-
bit PWM configuration, as a single 16-bit PWM timer, or a 16-
bit counter with two input capture channels. Each of the four
timer subsystems offer an 8-bit clock prescaler to accommo-
date a wide range of frequencies.
3.11
REAL-TIME TIMER AND WATCHDOG
The Timing and Watchdog Module (TWM) generates the
clocks and interrupts used for timing periodic functions in the
system. It also provides Watchdog protection against soft-
ware errors. The module operates on the slow system clock.
The real-time timer can generate a periodic interrupt to the
CPU at a software-programmed interval. This can be used
for real-time functions such as a time-of-day clock. The real-
time timer can trigger a wake-up condition from power-save
mode via the Multi-Input Wake-Up module.
The Watchdog is designed to detect program execution er-
rors such as an infinite loop or a “runaway” program. Once
Watchdog operation is initiated, the application program
must periodically write a specific value to a Watchdog regis-
ter, within specific time intervals. If the software fails to do so,
a Watchdog error is triggered, which resets the device.
3.12
USART
The USART supports a wide range of programmable baud
rates and data formats, and handles parity generation and
several error detection schemes. The baud rate is generated
on-chip, under software control.
There are two independent USARTs in the CR16MBR5 de-
vice and they offer a wake-up condition from the power-save
mode via the Multi-Input Wake-Up module.
3.13
The MICROWIRE/SPI (MWSPI) interface module supports
synchronous serial communications with other devices that
conform to MICROWIRE or Serial Peripheral Interface (SPI)
specifications. It supports 8-bit and 16-bit data transfers.
MICROWIRE/SPI
The MICROWIRE interface allows several devices to com-
municate over a single system consisting of four wires: serial
in, serial out, shift clock, and slave enable. At any given time,
the MICROWIRE interface operates as the master or a slave.
The CR16MBR5 supports the full set of slave select for multi-
slave implementation.
In master mode, the shift clock is generated on chip under
software control. In slave mode, a wake-up out of power-
save mode is triggered via the Multi-Input Wake-Up module.
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