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參數(shù)資料
| 型號： | CR16MPS9 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 105K |
| 代理商： | CR16MPS9 |
4
C
3.0
Device Overview
The CR16MBR5 CompactRISC microcontroller is a com-
plete microcomputer with all system timing, interrupt logic,
program memory, data memory, and I/O ports included on-
chip, making it well-suited to a wide range of embedded con-
troller applications. The block diagram on page 1 of the data
sheet shows the major on-chip components of the
CR16MBR5.
3.1
CR16B CPU CORE
The CR16MBR5 uses a CR16B CPU core module. This is
the same core used in other CompactRISC family member
designs, like DECT or GSM chipsets.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-per-
cycle pipelined system bus. As a result, the CPU can support
a peak execution rate of one instruction per clock cycle.
Compared with conventional RISC processors, the
CR16MBR5 differs in the following ways:
— The CPU core can use on-chip rather than external
memory. This eliminates the need for large and com-
plex bus interface units.
— Most instructions are 16 bits, so all basic instructions
are just two bytes long. Additional bytes are sometimes
required for immediate values, so instructions can be
two or four bytes long.
— Non-aligned word access is allowed. Each instruction
can operate on 8-bit or 16-bit data.
— The device is designed to operate with a clock rate in
the 10 to 25 MHz range rather than 100 MHz or more.
Most embedded systems face EMI and noise con-
straints that limit clock speed to these lower ranges. A
lower clock speed means a simpler, less costly silicon
implementation.
— The instruction pipeline uses three stages. A smaller
pipeline eliminates the need for costly branch predic-
tion mechanisms and bypass registers, while maintain-
ing adequate performance for typical embedded
controller applications.
For more information, please refer to the CR16B Program-
mer’s Reference Manual, Literature #: 633150.
3.2
MEMORY
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes. The CR16MBR5 implementa-
tion of this architecture uses only the lowest 128K bytes of
address space. Three types of on-chip memory occupy spe-
cific intervals within this address space:
32K bytes of flash EEPROM program memory
3K bytes of static RAM
2K bytes of EEPROM data memory with low endurance
(25K cycles)
128 bytes with high endurance (100K cycles)
The 3K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, depend-
ing on the instruction executed by the CPU. Each memory
access requires one clock cycle; no wait cycles or hold cycles
are required.
There are two types of flash EEPROM data memory storage.
The 2K bytes of EEPROM data memory with low endurance
(25K cycles) and 128 bytes of flash EEPROM data memory
with high endurance (100K cycles) are used for non-volatile
storage of data, such as configuration settings entered by the
end-user.
The 32K bytes of flash EEPROM program memory are used
to store the application program. It has security features to
prevent unintentional programming and to prevent unautho-
rized access to the program code.
3.3
INPUT/OUTPUT PORTS
The CR16MBR5 device has 56 software-configurable I/O
pins, organized into seven 8-pin ports called Port B, Port C,
Port F, Port G, Port H, Port I, and Port L. Each pin can be con-
figured to operate as a general-purpose input or general-pur-
pose output. In addition, many I/O pins can be configured to
operate as a designated input or output for an on-chip periph-
eral module such as the USART, timer, A/D converter, or MI-
CROWIRE/SPI interface.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input.
3.4
BUS INTERFACE UNIT
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules to the internal core bus. It determines
the configured parameters for bus access (such as the num-
ber of wait states for memory access) and issues the appro-
priate bus signals for each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are to be used when ac-
cessing flash EEPROM program memory, ISP memory and
the I/O area (Port B and Port C). Upon start-up the configu-
ration registers are set for slowest possible memory access.
To achieve fastest possible program execution, appropriate
values should be programmed. These settings vary with the
clock frequency and the type of on-chip device being access-
ed.
3.5
INTERRUPTS
The Interrupt Control Unit (ICU31L) receives interrupt re-
quests from internal and external sources and generates in-
terrupts to the CPU. An interrupt is an event that temporarily
stops the normal flow of program execution and causes a
separate interrupt service routine to be executed. After the in-
terrupt is serviced, CPU execution continues with the next in-
struction in the program following the point of interruption.
Interrupts from the timers, USARTs, MICROWIRE/SPI inter-
face, multi-input wake-up, and A/D converter are all
maskable interrupts; they can be enabled or disabled by the
software. There are 32 of these maskable interrupts, orga-
nized into 32 predetermined levels of priority.
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