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參數(shù)資料
| 型號： | CS2001YDWF20 |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHED CAPACITOR REGULATOR, 165 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | 0.300 INCH, SO-20 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 138K |
| 代理商： | CS2001YDWF20 |
3
Electrical Characteristics: 8V ≤ VBAT ≤ 16V, 8V ≤ VER ≤ 25V, 1mA ≤ IV(OUT) ≤ 100mA,
TTEST = –40°C to 125°C, unless otherwise specified.
CS2001
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Switching Regulator: continued
CPUMP
200
250
300
mV
Short detection threshold
Maximum Duty Cycle
80
95
%
VSW Leakage Current
IV(SW) @ VSW = 50V, SWSD = VOUT
100
A
s
Voltage Tripler
VBAT = 16V, IV(OUT) = –1mA, CCHG = 1.5F
Output Voltage Clamp
VER = 8V, IV(CHG) = –30A
6.25
8.00
13.00
V
VCHG – VER
VER = 12V, IV(CHG) = –90A
6.25
8.00
13.00
V
Initial Charge Time
CCHG = 0.15F, VER = 8V, VCHG = 14.25V
30
ms
Maximum Output Voltage
25
32.5
40
V
Clamp VCHG
Output Voltage Clamp VCHG
VER = 28V, IV(CHG) = 0A
25
32.5
40
V
Short Circuit Path Current
3mA
Limit VER to VCHG
s
RESETB OUTPUT
VBAT = 0V
High Threshold
VOUT increasing
4.525
4.750
4.850
V
Low Threshold
VOUT decreasing
4.500
4.650
4.825
V
Hysteresis
25
100
200
mV
Output Low Voltage
VOUT = 1.0V, IRESETB = 100A
0.5
V
IRESETB = 1mA, VOUT = 4.5V
0.5
V
Pull-Up Resistor
RESETB = 1V
25
50
100
k
s
SWSD INPUT
VBAT = 16V, VER = 25V, IV(OUT) = –1mA
High Threshold
0.7 × VOUT
V
Low Threshold
0.3 × VOUT
V
Input Impedance
referenced to ground
10
20
40
k
s
NERD OUTPUT
VBAT = 16V, IV(OUT) = –1mA, CNERD = 0.47F
VER Detection Voltage
1.5
6.5
V
Output Low Voltage
INERD = 1mA, VOUT = 4.5V
0.5
V
Pull-Up Current
NERD = 0.5V
30
40
50
A
Power on Delay
6.25
8.5
11
ms
Clamping Voltage (low)
VER present
1.00
1.25
1.50
V
Clamping Voltage (high)
VER not present
3.50
3.75
4.00
V
s
GENERAL
VER Load Current
VER = 25V, VBAT = 16V, IV(OUT) = –100mA
T = –40°C5
mA
T = 25°C5
mA
T = 125°C4
mA
Thermal Shutdown
(guaranteed by design)
160
210
°C
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