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參數(shù)資料
| 型號(hào)： | CS2540-7ERDDTB2 |
| 元件分類： | 電源模塊 |
| 英文描述： | 2-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | METAL, CASE S02, MODULE |
| 文件頁(yè)數(shù)： | 20/31頁(yè) |
| 文件大?。?/td> | 633K |
| 代理商： | CS2540-7ERDDTB2 |
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Cassette Style
100 Watt DC-DC Converters
S Series
Edition 1/01.2000
27/31
Table 17: Undervoltage monitor functions
Output type
Monitoring
Minimum adjustment range
Typical hysteresis
Uh [% of Ut]
JFET
NPN
U i
Uo1
of threshold level
U t
for
U t min...U t max
Uti
Uto
Uhi
Uho
D1
D5
no
yes
-
3.5...40 V 1
-
2.5...0.6
D2
D6
yes
no
Ui min...Ui max 1
-
3.4...0.4
-
D3
D7
yes
Ui min...Ui max 1
(0.95...0.985
Uo1) 2
3.4...0.4
"0"
D4
D8
no
yes
-
(0.95...0.985
Uo1) 2
-"0"
D0
D9
no
yes
-
3.5...40 V 3
-
2.5...0.6
yes
no
Ui min...Ui max 3 4
-
3.4...0.4
-
yes
Ui min...Ui max 3 4
3.5...40 V 3
3.4...0.4
2.5...0.6
yes
Ui min...Ui max 3 4
(0.95...0.985
Uo1) 2
3.4...0.4
"0"
-
DD
yes
Ui min...Ui max 1
3.5...40 V 1
3.4...0.4
2.5...0.6
1 Threshold level adjustable by potentiometer
2 Fixed value tracking if Uo1 is adjusted via R-input, option P or sense lines.
3 The threshold level permanently adjusted according to customer specification
±2% at 25°C. Any value within the specified range is
basically possible but causes a special type designation in addition to the standard option designations (D0/D9 respectively)!
4 Adjusted at Io nom
Fig. 30
Option D1...D0: JFET output, ID ≤ 2.5 mA
NPN output (D5...DD):
Connector pin D is internally connected via the collector-
emitter path of a NPN transistor to the negative potential of
output 1.
UD < 0.4 V (logic low) corresponds to a monitored
voltage level (
Ui and/or Uo1) > Ut +Uh. The current ID
through the open collector should not exceed 20 mA. The
NPN output is not protected against external overvoltages.
UD should not exceed 40 V.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
high, H,
ID ≤ 25 A at UD = 40 V
Ui and Uo1 > Ut + Uh
low, L,
UD ≤ 0.4 V at ID = 20 mA
Threshold tolerances and hysteresis:
If
Ui is monitored, the internal input voltage after the input
filter is measured. Consequently this voltage differs from
the voltage at the connector pins by the voltage drop
DUt i
across the input filter. The threshold levels of the D0 and D9
options are factory adjusted at nominal output current
Io nom
and at
TA = 25
°C. The value of DU
t i depends upon the input
voltage range (CS, DS, ..), threshold level
Ut, temperature
and input current. The input current is a function of the input
voltage and the output power.
Fig. 32
Definition of Ut i, DUt i and DUh i (JFET output)
JFET output (D0…D4):
Connector pin D is internally connected via the drain-
source path of a JFET (self-conducting type) to the nega-
tive potential of output 1.
UD ≤ 0.4 V (logic low) corresponds
to a monitored voltage level (
Ui and/or Uo1) < Ut. The cur-
rent
ID through the JFET should not exceed 2.5 mA. The
JFET is protected by a 0.5 W Zener diode of 8.2 V against
external overvoltages.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
low, L,
UD ≤ 0.4 V at ID = 2.5 mA
Ui and Uo1 > Ut + Uh
high, H,
ID ≤ 25 A at UD = 5.25 V
Vo1+
Vo1–
D
UD
ID
Rp
Input
11007
DUti
Uhi
UD low
UD
UD high
Ui
P
o
=
P
o
nom
P
o
=
0
P
o
=
0
Uti
P
o
=
P
o
nom
11021
Vo1+
Vo1–
D
UD
ID
Rp
Input
11006
Fig. 31
Option D5...DD: NPN output, Uo1
≤ 40 V, I
D
≤ 20 mA
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