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參數(shù)資料
| 型號(hào)： | CS3310-KSZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL VOL CTRL 2CH 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 音量控制 |
| 應(yīng)用： | 音頻系統(tǒng) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 配用： | 598-1000-ND - BOARD EVAL FOR CS3310 COL CTRL |
Micrel, Inc.
SY89645L
June 2011
3
M9999-060711
hbwhelp@micrel.com
Ordering Information
Part Number
Package Type
Operating Range
Package Marking
Lead Finish
SY89645LK4G
K4-20-1
Industrial
SY89645LK4G with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY89645LK4GTR
(2)
K4-20-1
Industrial
SY89645LK4G with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
Notes:
1.
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2.
Tape and Reel.
Pin Configuration
20-Pin TSSOP (K4-20-1)
Pin Description
Pin Number
Pin Name
Pin Function
1, 9, 13
GND
Power Supply Ground.
2
CLK_EN
Clock Enable. When LOW, Q outputs are forced low, /Q outputs are forced high. The synchronous
nature of the enable function forces the output clocks to enable or disable following a rising and a
falling edge of the input clock. When HIGH, clock outputs follow input clock. Internal 50k pull-up
resistor. VTH = VCC/2. See “Clock Enable (CLK_EN) Description” section.
3, 5, 6, 7, 8
NC
No Connect.
4
CLKIN
LVCMOS/LVTTL Clock Input. This is the input to the device. Input accepts single-ended input signals
as small as 1.2V. VTH = VCC/2. Internal 50k pull-down resistor.
10, 18
VCC
Positive Supply Pins. Connect to 3.3V supply, bypass with low ESR capacitors, as close to pins as
possible.
11, 12
14, 15
16, 17
19, 20
/Q3, Q3
/Q2, Q2
/Q1, Q1
/Q0, Q0
LVDS Differential Output Pairs: Differential buffered copies of the input signal. The output swing is
typically 280mV. Normally terminated with 100 across the output pairs (Q and /Q). See “LVDS
Output Termination” section.
or (408) 955-1690
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