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參數(shù)資料
| 型號： | CS3842A |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | IC AC/DC CONVERTER DUAL SIP16 |
| 中文描述： | 離線式電流模式PWM控制電路欠壓鎖定 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 156K |
| 代理商： | CS3842A |
5
C
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator com-
ponents.
Setting the Oscillator
Oscillator timing capacitor, C
T
, is charged by V
REF
through
R
T
and discharged by an internal current source. During
the discharge time, the internal clock signal blanks out the
output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times
are determined by the formula:
t
c
= R
T
C
T
ln
t
d
= R
T
C
T
ln
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 5.0V, V
upper
= 2.7V, V
lower
= 1.0V, I
d
= 8.3mA
t
c
≈
0.5534R
T
C
T
t
d
= R
T
C
T
ln
The frequency and maximum duty cycle can be deter-
mined using the Typical Performance Characteristic
graphs.
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd pin in a sin-
gle point ground.
The transistor and 5k
potentiometer, shown in the test
circuit, are used to sample the oscillator waveform and
apply an adjustable ramp to
Sense
.
)
2.3 - 0.0083 R
T
4.0 - 0.0083 R
T
(
)
V
REF
- I
d
R
T
- V
lower
V
REF
- I
d
R
T
- V
upper
(
)
V
REF
- V
lower
V
REF
- V
upper
(
V
REF
OSC
Gnd
R
T
C
T
Circuit Description: continued
V
OSC
Internal Clock
LARGE R
T
(
≈
10k
)
V
REF
Internal Clock
SMALL R
T
(
≈
700k
)
Sawtooth Mode
Triangular Mode
V
upper
V
lower
t
c
t
d
V
CC
I
OUT
V
OUT
Switch
Current
EA Output
V
OSC
OSC
RESET
Figure 2: Timing Diagram for key CS2841B parameters
Figure 3: Oscillator Timing Network and parameters
Timing parameters
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