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參數(shù)資料
| 型號： | CS4122XDWF24G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRIVER AIR CORE TRPL 24-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Jan/2008 |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC |
| 包裝： | 管件 |
CS4122
http://onsemi.com
7
Table 1. Nominal Output for Major Gauge (VBB = 14 V)
Input Code
(Decimal)
Ideal
Degrees
Nominal
Degrees
VSIN
(V)
VCOS
(V)
0
0.176
0.032
10.472
128
45
45.176
10.472
10.412
256
90
90.176
10.472
0.032
384
135
135.176
10.412
10.472
512
180
180.176
0.032
10.472
640
225
225.176
10.472
10.412
768
270
270.176
10.472
0.032
896
315
315.176
10.476
10.412
1023
359.65
359.826
0.032
10.472
Table 2. Nominal Output for Minor Gauges (VBB = 14 V)
Input Code
(Decimal)
Scale
Degrees
from Center
VCOIL
0
56.1
10.417
127
55.88
0.22
0.027
128
56.32
0.22
0.027
255
112.2
56.1
10.417
The 12 bits are shifted into the device’s shift register MSB
first using a SPI compatible scheme. This method is shown
which the data is intended. The CS must be high and remain
high for SCLK to be enabled. Data on SI is shifted in on the
rising edge of the synchronous clock signal. Data in the shift
register is shifted to SO on the falling edge of SCLK. This
arrangement allows the cascading of devices. SO is always
enabled. Data shifts through without affecting the outputs
until CS is brought low. At this time, the internal DAC is
updated and the outputs change accordingly.
CS
SI
SCLK
SO
SI(Setup)
SI(Hold)
SO(tpd)
SO(Rise, Fall)
10% 90%
CSHold
CSSetup
Figure 7. Serial Data Timing Diagram
The DAC for the major gauge driver outputs 128 discrete
levels selected by bits D6 D0. These bits are XOR’d with
D7 to invert them when choosing the 2nd half of each
quadrant (each odd octant). This reduces the number of
resistors and switches required. The MUX chooses which
signals to send to the output amplifiers based upon D9 D7.
There are three choices for each amplifier: high, low or the
DAC output.
The DAC’s for the minor gauge drivers similarly output
128 discrete levels selected by bits D6 D0. These bits are
also XOR’d with D7 to invert them when choosing the 2nd
half of the output range. The MUX chooses which signals to
send to the output amplifiers based upon D7. There are two
choices for each amplifier; high or the DAC output. Bits D8
and D9 are not used, but should be set to “00” to ensure that
the minor gauge outputs are enabled.
The output buffers are unity gain amplifiers. Each of the
eight outputs are designed to swing close to the supply rails
to maximize the voltage across the coils to produce
maximum torque. Additionally, this lowers the power
dissipation. The current for each output is also monitored. If
any of the major gauge outputs exceed the maximum value,
all of the major outputs are disabled. If any of the minor
gauge outputs exceed the maximum value, all of the minor
outputs are disabled. The falling edge of the CS reenables
the outputs with the fault condition but they remain on only
if the overcurrent situation has been eliminated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4122XDWFR24 | 功能描述:馬達(dá)/運(yùn)動/點(diǎn)火控制器和驅(qū)動器 Air Core Gauge DRVR RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube |
| CS4122XDWFR24G | 功能描述:馬達(dá)/運(yùn)動/點(diǎn)火控制器和驅(qū)動器 Air Core Gauge DRVR w/Serial Bus Input RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube |
| CS4124 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:High Side PWM FET Controller |
| CS4124/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Side PWM FET Controller |
| CS-4124N16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DC Motor Controller/Driver |
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