參數(shù)資料
型號: CS4338-KSZ
廠商: Cirrus Logic Inc
文件頁數(shù): 6/25頁
文件大?。?/td> 0K
描述: IC DAC 24BIT 96KHZ 96DB 8-SOIC
標(biāo)準(zhǔn)包裝: 100
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 104mW
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 96k
產(chǎn)品目錄頁面: 756 (CN2011-ZH PDF)
其它名稱: 598-1048-5
14
CS4334/5/8/9
4.3
De-Emphasis
The CS4334 family includes on-chip digital de-emphasis. Figure 9 shows the de-emphasis curve for Fs
equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes
in sample rate, Fs.
The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges
of LRCK. This function is available only in the internal serial clock mode.
4.4
Initialization and Power-Down
The Initialization and Power-Down sequence flow chart is shown in Figure 14. The CS4334 family enters
the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are reset,
and the internal voltage reference, one-bit digital-to-analog converters and switched-capacitor low-pass fil-
ters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK are present.
Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine
the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is
applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent
voltage, VQ.
4.5
Output Transient Control
The CS4334 family uses Popguard technology to minimize the effects of output transients during power-
up and power-down. This technique eliminates the audio transients commonly produced by single-ended
single-supply converters when it is implemented with external DC-blocking capacitors connected in series
with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Af-
ter a short delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent
voltage, VQ. Approximately 10,000 sample cycles later, the outputs reach VQ and audio output begins. This
gradual voltage ramping allows time for the external DC-blocking capacitor to charge to VQ, effectively
blocking the quiescent DC voltage.
To prevent transients at power-down, the device must first enter its power-down state. This is accomplished
by removing MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are dis-
connected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR
which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to
the device may be turned off, and the system is ready for the next power-on.
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before
turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur
when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
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