參數(shù)資料
型號(hào)： CS4338-KSZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 5/25頁(yè)
文件大?。?/td> 0K
描述： IC DAC STER 24BIT 96KHZ 8-SOIC
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 104mW
工作溫度： -10°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 2 電壓，單極
采樣率（每秒）： 96k
13
CS4334/5/8/9
4. SYSTEM DESIGN
The CS4334 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in BRM and 96, 88.2
and 64 kHz in HRM. Audio data is input via the serial data input pin (SDATA). The Left/Right Clock (LRCK) defines
the channel and delineation of data, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The
CS4334/5/8/9 differ in serial data formats as shown in Figures 10-13.
4.1
Master Clock
MCLK must be either 256x, 384x or 512x the desired input sample rate in BRM and either 128x or 192x the
desired input sample rate in HRM. The LRCK frequency is equal to Fs, the frequency at which words for
each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during
the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal
dividers are set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and
the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK,
LRCK and SCLK must be synchronous.
Table 1. Common Clock Frequencies
4.2
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4334 family supports both
external and internal serial clock generation modes. Refer to Figures 10-13 for data formats.
4.2.1
External Serial Clock Mode
The CS4334 family will enter the External Serial Clock Mode when 16 low to high transitions are detected
on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Se-
rial Clock Mode and de-emphasis filter cannot be accessed. The CS4334 family will switch to Internal Se-
rial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames
of LRCK. Refer to Figure 14.
4.2.2
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data format. Operation in
this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows
access to the digital de-emphasis function. Refer to Figures 10 - 14 for details.
LRCK
(kHz)
MCLK (MHz)
HRM
BRM
128x
192x
256x
384x
512x
32
4.0960
6.1440
8.1920 12.2880 16.3840
44.1
5.6448
8.4672 11.2896 16.9344 22.5792
48
6.1440
9.2160 12.2880 18.4320 24.5760
64
8.1920 12.2880
-
88.2
11.2896 16.9344
-
96
12.2880 18.4320
-
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