參數(shù)資料
型號: CS48DV2B-DQZR
廠商: Cirrus Logic Inc
文件頁數(shù): 8/26頁
文件大小: 0K
描述: IC DSP AUDIO 32BIT 2CH 48-LQFP
標準包裝: 2,000
系列: CS48DV2
類型: 定點
接口: I²C,SPI
時鐘速率: 150MHz
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
16
Copyright 2009 Cirrus Logic
DS875F2
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
D
ELPHI
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode
Figure 5. Serial Control Port - I2C Slave Mode Timing
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow of the input data buffer.
fiicck
-
400
kHz
SCP_CLK low time
tiicckl
1.25
-
s
SCP_CLK high time
tiicckh
1.25
-
s
SCP_CLK rising to SCP_SDA rising or falling for
START or STOP condition
tiicckcmd
1.25
s
START condition to SCP_CLK falling
tiicstscl
1.25
-
s
SCP_CLK falling to STOP condition
tiicstp
2.5
-
s
Bus free time between STOP and START conditions
tiicbft
3-
s
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
ns
Hold time SCP_SDA input after SCP_CLK falling
tiich
20
-
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
-18
ns
SCP_CLK falling to SCP_IRQ rising
tiicirqh
-3*DCLKP + 40
ns
NAK condition to SCP_IRQ low
tiicirql
3*DCLKP + 20
ns
SCP_CLK rising to SCB_BSY low
tiicbsyl
-3*DCLKP + 20
ns
SCP_BSY
SCP_CLK
SCP_SDA
SCP_IRQ
0
1
6780
1
7
tiicckl
tiicckh
tiicsu
tiich
A6
A0
R/W
ACK
LSB
tiicirqh
tiicirql
8
ACK
MSB
tiicstp
6
tiiccbsyl
tiicdov
tiicbft
tiicstscl
tiicckcmd
fiicck
tiicckcmd
tiicf
tiicr
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