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參數(shù)資料
| 型號(hào)： | CS5112EDWFR24 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | 1.4A Switching Regulator with 5V, 100mA Linear Regulator with Watchdog, RESET and ENABLE |
| 中文描述： | 1.4A的開(kāi)關(guān)穩(wěn)壓器采用5V，100mA的線(xiàn)性穩(wěn)壓器，帶有看門(mén)狗，復(fù)位和啟用 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | CS5112EDWFR24 |
8
Application Notes: continued
C
Step 4
Determine the maximum on time at the minimum oscilla-
tor frequency and V
IN
. For discontinuous operation, all of
the stored energy in the inductor is transferred to the load
prior to the next cycle. Since the current through the
inductor cannot change instantaneously and the induc-
tance is constant, a volt-second balance exists between the
on time and off time. The voltage across the inductor dur-
ing the on cycle is V
IN
and the voltage across the inductor
during the off cycle is V
OUT
- V
IN
. Therefore:
V
IN
t
on
= (V
OUT
-V
IN
)t
off
(4a)
where the maximum on time is:
[
t
on(max)
.
(4b)
Step 5
Calculate the maximum inductance allowed for discontin-
uous operation:
L
(max)
=
(5)
where
h
= efficiency.
Usually
h
= 0.75 is a good starting point. The ICs power
dissipation should be calculated after the peak current has
been determined in Step 6. If the efficiency is less than
originally assumed, decrease the efficiency and recalculate
the maximum inductance and peak current.
Step 6
Determine the peak inductor current at the minimum
inductance, minimum V
IN
and maximum on time to make
sure the inductor current doesnt exceed 1.4A.
I
pk
=
(6)
Step 7
Determine the minimum output capacitance and maxi-
mum ESR based on the allowable output voltage ripple.
C
OUT(min)
=
(7a)
ESR
(min)
=
(7b)
In practice, it is normally necessary to use a larger capaci-
tance value to obtain a low ESR. By placing capacitors in
parallel, the equivalent ESR can be reduced.
Step 8
Compensate the feedback loop to guarantee stability
under all operating conditions. To do this, we calculate the
modulator gain and the feedback resistor network attenu-
ation and set the gain of the error amplifier so that the
overall loop gain is 0dB at the crossover frequency, f
CO
. In
addition, the gain slope should be -20dB/decade at the
crossover frequency.
The low frequency gain of the modulator (i.e. error ampli-
fier output to output voltage) is:
=
,
(8a)
where
I
pk(max)
=
=
=2.3A.
The V
OUT
/V
EA
transfer function has a pole at:
f
p
= 1/(1R
Load
C
OUT
) ,
(8b)
and a zero due to the output capacitors ESR at:
f
z
= 1/(21ESR C
OUT
).
(8c)
Since the error amplifier reference voltage is 1.25V, the
output voltage must be divided down or attenuated
before being applied to the input of the error amplifier.
The feedback resistor divider attenuation is:
.
The error amplifier in the CS5112 is an operational transcon-
ductance amplifier (OTA), with a gain given by:
G
OTA
= gmZ
OUT
(8d)
where:
gm =
.
(8e)
For the CS5112, gm = 2700μA/V typical.
One possible error amplifier compensation scheme is
shown in Figure 9. This gives the error amplifier a gain
plot as shown in Figure 10.
For the error amplifier gain shown in Figure 10, a low fre-
quency pole is generated by the error amplifier output
impedance and C
1
. This is shown by the line AB with a -
20dB/decade slope in Figure 12. The slope changes to zero
at point B due to the zero at:
f
z
= 1/(21R
4
C
1
).
(8f)
Figure 9. RC network used to compensate the error amplifier (OTA).
V
OUT
V
FB1
V
FB2
M
U
X
SELECT
Error
Amplifier
1.25V
+
D
C1
R4
C2
R1
R2
R3
I
OUT
V
IN
1.25V
V
OUT
(2.4V)/(7)
150m
V
EA(max)
/G
CSA
R
S
R
Load
L f
2
I
pk(max)
V
EA(max)
V
OUT
V
EA
V
ripple
I
pk
I
pk
8fV
ripple
V
IN(min)
t
on(max)
L
(min)
f
SW(min)
V
IN2(min)
t
on2(max)
2 P
OUT
/
h
]
1
f
SW(min)
[
1 - V
IN(min)
V
OUT(max)
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