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參數(shù)資料
| 型號： | CS5124XDR8 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | High Performance, Integrated Current Mode PWM Controllers |
| 中文描述： | 高性能，集成電流模式PWM控制器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 172K |
| 代理商： | CS5124XDR8 |
Package Lead Description
PACKAGE LEAD #
8 Lead SO Narrow
CS5124
1
2
LEAD SYMBOL
FUNCTION
C
4
Electrical Characteristics: -40°C
≤
T
J
≤
125°C, -40°C
≤
T
A
≤
105°C, 7.60V
≤
V
CC
≤
20V, UVLO = 3.0V, I
SENSE
= 0V,
C
V(CC)
= 0.33μF, C
GATE
= 1nF (ESR = 10
), C
SS
= 470pF C
V(FB)
= 100pF
,
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS5126
1
-
V
CC
BIAS
V
CC
Power Input Pin.
V
CC
Clamp Output Pin. This pin will control the gate of an N-channel MOS-
FET that in turn regulates V
CC
. This pin is internally clamped at 15V when
the IC is in sleep mode.
Clock Synchronization Pin. A positive edge will terminate the current PWM
cycle. Ground this pin when it is not used.
Sleep and under voltage lockout pin. A voltage greater than 1.8V causes the
chip to "wake up" however the GATE remains low. A voltage greater than
2.6V on this pin allows the output to switch.
Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is
charged with 10μA and discharged with 10mA. The Soft Start capacitor con-
trols both soft-start time and hiccup mode frequency.
Voltage Feedback Pin. The collector of an optocoupler is typically tied to this
pin. This pin is pulled up internally by a 4.3k
resistor to 5V and is clamped
internally at 2.9V(2.65V). If V
FB
is pulled > 4V, the oscillator is disabled and
GATE will stay high. If the V
FB
pin is pulled < 0.49V, GATE will stay low.
Current Sense Pin. This pin is connected to the current sense resistor on the
primary side. If V
FB
is floating, the GATE will go low if I
SENSE
= 195mV
(335mV). If I
SENSE
> 275mV (525mV), Soft Start will be initiated.
Gate Drive Output Pin. Capable of driving a 3nF load. GATE is nominally
clamped to 13.5V.
Ground Pin.
-
3
SYNC
3
2
UVLO
4
4
SS
5
5
V
FB
6
6
I
SENSE
7
7
GATE
8
8
Gnd
I
Voltage Feedback
V
FB
Pull-up Res.
V
FB
Clamp Voltage
V
FB
Clamp Voltage
V
FB
Fault Voltage Threshold
2.9
2.63
2.40
460
4.3
2.90
2.65
490
8.1
3.15
2.90
520
k
V
V
mV
CS5124 Only
CS5126 Only
I
Output Gate Drive
Maximum Sleep
Pull-down Voltage
GATE High (AC)
GATE Low (AC)
GATE High Clamp Voltage
Rise Time
V
CC
= 6.0V, I
OUT
= 1mA
1.2
2.0
V
Series resistance < 1
(Note 1)
Series resistance < 1
(Note 1)
V
CC
= 20V
Measure GATE rise time,
1V < GATE < 9V; V
CC
=12V
Measure GATE fall time,
9V > GATE > 1V; V
CC
= 12V
V
CC
-1
V
CC
-0.5
0.0
13.5
45
V
V
V
ns
0.5
16.0
65
11.0
Fall Time
25
55
ns
I
Thermal Shutdown
Thermal Shutdown Temperature (Note 1) (GATE low)
Thermal Enable Temperature
Thermal Hysteresis
Notes
1. Not tested in production. Specification is guaranteed by design.
135
100
15
150
125
25
165
150
35
°C
°C
°C
(Note 1) (GATE switching)
(Note 1)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS5124XDR8G | 功能描述:電流型 PWM 控制器 Hi Performance Current Mode PWM RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| CS5126-KL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS5126-KLZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS5126-KP | 制造商:Rochester Electronics LLC 功能描述:2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, - Bulk |
| CS5126XDR8 | 功能描述:IC REG CTRLR FLYBK ISO PWM 8SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
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