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參數(shù)資料
| 型號： | CS5127GDWR16 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Dual Output Nonsynchronous Buck Controller with Sync Function and Second Channel Enable |
| 中文描述： | 非同步雙輸出同步降壓控制器的功能及第二通道啟用 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | CS5127GDWR16 |
C
6
Theory of Operation: continued
mode controller relies on a change in the error signal to
indicate a change in the line and/or load conditions. The
error signal change causes the error loop to respond with a
correction that is dependent on the gain of the error ampli-
fier. A current mode controller has a constant error signal
during line transients, since the slope of the ramp signal
will change in this case. However, regulation of load tran-
sients still requires a change in the error signal. V
2
a
control maintains a fixed error signal for both line and
load variation, since the ramp signal is affected by both.
The CS5127 can be operated in voltage mode if necessary.
For example, if very small values of output ripple voltage
are required, V
2
acontrol may not operate correctly.
Details on how to choose the components for voltage
mode operation are provided in the section on V
FFB
com-
ponent selection.
As output line and load conditions change, the V
2
acon-
trol loop modifies the switch duty cycle to regulate the
output voltage. The CS5127 uses a fixed frequency archi-
tecture. Both output channels are controlled from a
common oscillator. The CS5127 can typically provide a
maximum duty cycle of about 90%.
It is sometimes desirable to shift the switching noise spec-
trum to different frequencies. A pulse train applied to the
SYNC lead will terminate charging of the C
T
lead capacitor
and pull the C
T
lead voltage to ground for the duration of
the positive pulse level. This reduces the period of oscilla-
tion and increases the switching frequency.
Synchronization must always be done at a frequency
higher than the typical oscillator frequency. Using a lower
frequency will lead to erratic operation and poor regula-
tion. The SYNC pulse train frequency should be at least 10
% higher than the unsynchronized oscillator frequency.
Synchronizing the oscillator will also decrease the maxi-
mum duty cycle. If the nominal oscillator frequency is
200kHz, increasing the oscillator frequency by 10% (to
220kHz) will decrease the maximum duty cycle from a
typical of 90% to about 89%. Increasing the frequency by
25% (to 250kHz) will change the maximum duty cycle to
about 87%. A 50% increase (to 300kHz) gives a maximum
duty cycle of about 85%. The width of the SYNC pulse
should be slightly shorter than the duration of the falling
edge of the C
T
lead waveform (see Figure 2a) so the SYNC
pulse doesnt interfere with the oscillator function.
Figure 2a: Sync pulse duration vs. C
T
lead discharge time.
The best way to determine if the pulse width is sufficiently
short is to examine the C
T
lead waveform with an oscillo-
scope. If òdead spotsó are observed in the C
T
lead waveform,
decreasing the SYNC pulse width should be considered.
Alternatively, the SYNC signal may be AC coupled through
a small capacitor. In this case, care must be taken to ensure
that current pulled out of the IC during the high-to-low tran-
sition of the SYNC signal is limited to less than 5mA.
Figure 2b: Capacitive coupling of the SYNC signal. The external diode
is used to clamp the IC substrate diode if I
is greater than 5mA
during the negative portion of the input waveform.
The CS5127 has no on-board current limit circuitry. An
example current limit circuit is provided in the Additional
Application Circuits section of this data sheet.
Overcurrent Protection
Oscillator
SYNC
20k
2200p
C
T
Lead Waveform
Sync Lead Waveform
If the sync pulse is longer
than the C
T
lead discharge
time, a short òdead spotó
will exist during which the
output driver is off.
Sync Function
Constant Frequency
Voltage Mode Control
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