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參數(shù)資料
| 型號： | CS51312GDR16 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Synchronous CPU Buck Controller for 12V Only Applications |
| 中文描述： | 同步降壓控制器的CPU，只有應用的12V |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 276K |
| 代理商： | CS51312GDR16 |
where
P
CIN(RMS)
= input capacitor RMS power dissipation;
I
CIN(RMS)
= total input RMS current;
ESR
CIN
= total input capacitor ESR.
Step 6: Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving
this is by using an input inductor and a bypass capacitor.
The input inductor isolates the supply from the noise gen-
erated in the switching portion of the buck regulator and
also limits the inrush current into the input capacitors
upon power up. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients. The worst case is when the load changes
from no load to full load (load step), a condition under
which the highest voltage change across the input capaci-
tors is also seen by the input inductor. The inductor suc-
cessfully blocks the ripple current while placing the tran-
sient current requirements on the input bypass capacitor
bank, which has to initially support the sudden load
change.
The minimum inductance value for the input inductor is
therefore:
L
IN
=
,
where
L
IN
= input inductor value;
V = voltage seen by the input inductor during a full
load swing;
(dI/dt)
MAX
= maximum allowable input current slew
rate.
The designer must select the LC filter pole frequency so
that at least 40dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double-pole net-
work with a slope of
2, a roll-off rate of –40dB/dec, and a
corner frequency:
f
C
=
,
where
L = input inductor;
C = input capacitor(s).
Step 7: Selection of the Power FET
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons:
1) Its very high input impedance;
and
2) Its very
fast switching times.
The electrical characteristics of a MOS-
FET are considered to be those of a perfect switch. Control
and drive circuitry power is therefore reduced. Because the
input impedance is so high, it is voltage driven. The input
of the MOSFET acts as if it were a small capacitor, which
the driving circuit must charge at turn on. The lower the
drive impedance, the higher the rate of rise of V
GS
, and the
faster the turn- on time. Power dissipation in the switching
MOSFET consists of 1) conduction losses, 2) leakage losses,
3) turn-on switching losses, 4) turn-off switching losses,
and 5) gate-transitions losses. The latter three losses are
proportional to frequency. For the conducting power dissi-
pation rms values of current and resistance are used for
true power calculations. The fast switching speed of the
MOSFET makes it indispensable for high-frequency power
supply applications. Not only are switching power losses
minimized, but also the maximum usable switching fre-
quency is considerably higher. Switching time is indepen-
dent of temperature. Also, at higher frequencies, the use of
smaller and lighter components (transformer, filter choke,
filter capacitor) reduces overall component cost while
using less space for more efficient packaging at lower
weight.
The MOSFET has purely capacitive input impedance. No
DC current is required. It is important to keep in mind the
drain current of the FET has a negative temperature coeffi-
cient. Increase in temperature causes higher on-resistance
and greater leakage current. V
DS(ON)
should be low to min-
imize power dissipation at a given I
D
, and V
GS
should be
high to accomplish this. MOSFET switching times are
determined by device capacitance, stray capacitance, and
the impedance of the gate drive circuit. Thus the gate driv-
ing circuit must have high momentary peak current sourc-
ing and sinking capability for switching the MOSFET. The
input capacitance, output capacitance and reverse-transfer
capacitance also increase with increased device current rat-
ing.
Two considerations complicate the task of estimating
switching times. First, since the magnitude of the input
capacitance, C
ISS
, varies with V
DS
, the RC time constant
determined by the gate-drive impedance and C
ISS
changes
during the switching cycle. Consequently, computation of
the rise time of the gate voltage by using a specific gate-
drive impedance and input capacitance yields only a rough
estimate. The second consideration is the effect of the
“Miller” capacitance, C
RSS
, which is referred to as C
DG
in
the following discussion. For example, when a device is on,
V
DS(ON)
is fairly small and V
GS
is about 12V. C
DG
is
charged to V
DS(ON)
V
GS
, which is a negative potential if
the drain is considered the positive electrode. When the
drain is “off”, C
DG
is charged to quite a different potential.
In this case the voltage across C
DG
is a positive value since
the potential from gate-to-source is near zero volts and V
DS
is essentially the drain supply voltage. During turn-on and
turn-off, these large swings in gate-to-drain voltage tax the
current sourcing and sinking capabilities of the gate drive.
In addition to charging and discharging C
GS
, the gate drive
must also supply the displacement current required by
C
DG
(I
GATE
= C
dg
dV
dg
/dt). Unless the gate-drive
impedance is very low, the V
GS
waveform commonly
plateaus during rapid changes in the drain-to-source volt-
age.
The most important aspect of FET performance is the Static
Drain-To-Source On-Resistance (R
DS(ON)
), which effects
regulator efficiency and FET thermal management require-
ments. The On-Resistance determines the amount of cur-
rent a FET can handle without excessive power dissipation
that may cause overheating and potentially catastrophic
failure. As the drain current rises, especially above the con-
tinuous rating, the On-Resistance also increases. Its posi-
tive temperature coefficient is between +0.6%/C and
+0.85%/C. The higher the On-Resistance the larger the
conduction loss is. Additionally, the FET gate charge
should be low in order to minimize switching losses and
reduce power dissipation.
Both logic level and standard FETs can be used.
1
2
π
LC
V
(dI/dt)
MAX
Application Information: continued
13
C
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