IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERAT" />
參數(shù)資料
型號(hào): CS5381-KSZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 3/16頁(yè)
文件大?。?/td> 0K
描述: IC ADC AUD 120DB 192KHZ 24-SOIC
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 216k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 445mW
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
配用: 598-1592-ND - REFERENCE DESIGN CS5381 AUD ADC
598-1008-ND - BOARD EVAL FOR CS5381 192KHZ ADC
IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERATOR
11
ICS843031AG-01 REV. A NOVEMBER 11, 2008
ICS843031-01
FEMTOCLOCKS CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50
Ω load, and a termination
voltage of V
CC
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
– V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CC_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.9V)/50
Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L
] * (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50
Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC - 2V
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