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參數(shù)資料
| 型號(hào)： | CS5532-ASZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 22/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CH W/LNA 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極；2 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1159-ND - BOARD EVAL FOR CS5532U ADC |
| 其它名稱： | 598-1112-5 |
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CS5531/32/33/34-AS
DS289F5
29
U/B (Unipolar / Bipolar) [22] [6]
0
Select Bipolar mode.
1
Select Unipolar mode.
OL1-OL0 (Output Latch Bits) [21:20] [5:4]
The latch bits will be set to the logic state of these bits upon command word execution when the output
latch select bit (OLS) in the configuration register is logic 0. Note that the logic outputs on the chip are
powered from VA+ and VA-.
00
A0 = 0, A1 = 0
01
A0 = 0, A1 = 1
10
A0 = 1, A1 = 0
11
A0 = 1, A1 = 1
DT (Delay Time Bit) [19] [3]
When set, the converter will wait for a delay time before starting a conversion. This allows settling time for
A0 and A1 outputs before a conversion begins. The delay time will be 1280 MCLK cycles when FRS = 0,
and 1536 MCLK cycles when FRS = 1.
0
Begin Conversions Immediately.
1
Wait 1280 MCLK cycles (FRS = 0) or 1536 MCLK cycles (FRS = 1) before starting conversion.
OCD (Open Circuit Detect Bit) [18] [2]
When set, this bit activates a 300 nA current source on the input channel (AIN+) selected by the channel
select bits. Note that the 300nA current source is rated at 25°C. At -55°C, the current source doubles to
approximately 600 nA. This feature is particularly useful in thermocouple applications when the user wants
to drive a suspected open thermocouple lead to a supply rail.
0
Normal mode.
1
Activate current source.
OG1-OG0 (Offset / Gain Register Pointer Bits) [17:16] [1:0]
These bits are only used when OGS in the Configuration Register is set to ‘1’. They allow the user to select
the offset and gain register to use while performing a conversion or calibration. When the OGS bit in the
Configuration Register is set to ‘0’, the offset and gain register for the referenced physical channel (CS1-
CS0 bits of the Setup) will be used.
00
Use offset and gain register from physical channel 1
01
Use offset and gain register from physical channel 2
10
Use offset and gain register from physical channel 3
11
Use offset and gain register from physical channel 4
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參數(shù)描述 |
|---|---|
| CS5532-ASZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5532-BS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 2-Ch 24-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5532-BSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5532-BSZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 2-Ch 24-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5532-BSZ/H | 制造商:Cirrus Logic 功能描述: |
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