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參數(shù)資料
| 型號： | CS8130-CSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC IR TRANSCEIVER 2-5V 20-SSOP |
| 標準包裝： | 66 |
| 類型： | 收發(fā)器 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 758 (CN2011-ZH PDF) |
| 配用： | 598-1161-ND - BOARD EVAL FOR CS8130 |
| 其它名稱： | 598-1204-5 |
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Reset
Bringing the RESET pin low will force the inter-
nal logic, including the control registers, into a
known state, provided the PWRDN pin is high.
RESET is disabled if the PWRDN pin is low.
The reset state is given in each register definition
table. RESET must be low for >25 ms if using
the crystal oscillator (see Clock Generation
above).
Control Register Definitions
The various control registers within the CS8130
may be written by setting the D/C pin to low,
and sending characters from the UART to the
TXD pin. The characters are interpreted as a 4-
bit address field and a 4-bit data field, as shown
in Figure 7. After the control character is re-
ceived and written into the control register, it is
optionally echoed back out the RXD pin. The
baud rate used for this control mode is whatever
is currently set in the baud rate register. If the
"load baud rate" bit is written to, then the new
baud rate takes effect after the character has been
echoed back, if echo is enabled. Otherwise, the
new baud rate is effective immediately.
One of the control registers contains a shadow
register set enable bit, which effectively becomes
the MSB of the 5-bit register address. Hence
there are 31 4-bit registers. The shadow bit must
be written to a 1 to allow access to the registers
with addresses 16 through 31. The shadow bit
register is always accessible, independent of the
state of the shadow bit. The shadow bit must be
written to 0 to enable access to registers 0
through 15.
The following tables define the detailed function
of all the registers inside the CS8130.
CD0
CD1
CD2
CD3
AD0
AD1
AD2
AD3
CD0
CD1
CD2
CD3
AD0
AD1
AD2
AD3
Start
Bit
Data
Address
Stop
Bit
Start
Bit
Data
Address
Stop
Bit
TXD
D/C
RXD
Figure 7. Control Mode Timing
CS8130
12
DS134PP2
CS8130
12
DS134F1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8130-CSZR | 功能描述:紅外收發(fā)器 IC Multi-Standard Infrared Transceiver RoHS:否 制造商:Vishay Semiconductors 波長:900 nm 連續(xù)數(shù)據(jù)傳輸:115.2 Kbit/s 傳輸距離:1 m 輻射強度:60 mW/sr 半強度角度:44 deg 脈沖寬度:2 us 最大上升時間:100 ns 最大下降時間:100 ns LED 電源電壓:- 0.5 V to 6 V 最大正向電流:80 mA 工作電壓:2.4 V to 5.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 尺寸:6 mm x 3.1 mm x 1.9 mm 封裝 / 箱體: 封裝:Reel |
| CS8130-IS | 制造商:Cirrus Logic 功能描述:IRDA TX/RX 0.1152MBPS 2.7V TO 5.5V 20SSOP - Rail/Tube |
| CS8130-ISR | 制造商:Cirrus Logic 功能描述:IRDA TX/RX 0.1152MBPS 2.7V TO 5.5V 20SSOP - Tape and Reel |
| CS8135 | 制造商:CHERRY 制造商全稱:CHERRY 功能描述:5V, 5V Low Dropout Dual Regulator with /ENABLE RESET |
| CS-8135 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V 5V Low Dropout Dual Regulator with Reset/Enable |
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