VREG F" />
參數(shù)資料
型號: CS8190EDWF20G
廠商: ON Semiconductor
文件頁數(shù): 9/11頁
文件大?。?/td> 0K
描述: IC TACH/SPEEDO DRVR PREC 20SOICW
產(chǎn)品變化通告: 1Q2012 Discontinuation 30/Mar/2012
標準包裝: 38
類型: 驅(qū)動器
應(yīng)用: 自動
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 管件
CS8190
http://onsemi.com
7
Figure 7. Partial Schematic of Input and Charge Pump
VREG
FREQIN
SQOUT
R3
2.0 V
QSQUARE
CCP
R4
VC(t)
CP+
Q1
Q2
Q3
0.25 V
2.0 V
CP
RT
C4
F/VOUT
F to V
+
+
+
Figure 8. Timing Diagram of FREQIN and ICP
VREG
FREQIN
SQOUT
0
ICP+
tCHG
T
VCP+
0
VCC
tDCHG
Ripple voltage on the F/V output causes pointer or needle
flutter especially at low input frequencies.
The response time of the F/V is determined by the time
constant formed by RT and C4. Increasing the value of C4
will reduce the ripple on the F/V output but will also increase
the response time. An increase in response time causes a
very slow meter movement and may be unacceptable for
many applications.
The CS8190 has an undervoltage detect circuit that disables
the input comparator when VCC falls below 8.0 V(typical).
With no input signal the F/V output voltage decreases and the
needle moves towards zero. A second undervoltage detect
circuit at 6.0 V(typical) causes the function generator to
generate a differential SIN drive voltage of zero volts and the
differential COS drive voltage to go as high as possible. This
combination of voltages (Figure 2) across the meter coil
moves the needle to the 0
° position. Connecting a large
capacitor(> 2000
mF) to the VCC lead (C2 in Figure 9)
increases the time between these undervoltage points since
the capacitor discharges slowly and ensures that the needle
moves towards 0
° as opposed to 360°. The exact value of the
capacitor depends on the response time of the system,the
maximum meter deflection and the current consumption of
the circuit. It should be selected by breadboarding the design
in the lab.
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