參數(shù)資料
型號(hào): CS8363YDPS7
英文描述: VOLT REGULATOR|FIXED/ADJUSTABLE|+3.3V|+3.3/20V|BIPOLAR|SIP|7PIN|PLASTIC
中文描述: 電壓調(diào)節(jié)器|固定/可調(diào)| 3.3 | 3.3/20V |雙極|園區(qū)| 7PIN |塑料
文件頁數(shù): 4/8頁
文件大?。?/td> 65K
代理商: CS8363YDPS7
CS8363
http://onsemi.com
4
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
D
2
PAK
PIN SYMBOL
FUNCTION
1
V
STBY
Standby output voltage delivering 100 mA.
2
V
IN
Input voltage.
3
V
TRK
Tracking output voltage controlled by ENABLE delivering 250 mA.
4
GND
Reference ground connection.
5
Adj
Resistor divider from V
TRK
to Adj. Sets the output voltage on V
TRK
. If tied to
V
TRK
, V
TRK
will track V
STBY
.
6
ENABLE
Provides on/off control of the tracking output, active LOW.
7
RESET
CMOS compatible output lead that goes low whenever V
STBY
falls out of
regulation.
CIRCUIT DESCRIPTION
ENABLE Function
The ENABLE function switches the output transistor for
V
TRK
on and off. When the ENABLE lead voltage exceeds
1.4 V (typ), V
TRK
turns off. This input has several hundred
millivolts of hysteresis to prevent spurious output activity
during power–up or power–down.
RESET Function
The RESET is an open collector NPN transistor,
controlled by a low voltage detection circuit sensing the
V
STBY
(3.3 V) output voltage. This circuit guarantees the
RESET output stays below 1.0 V (0.1 V typ) when V
STBY
is as low as 1.0 V to ensure reliable operation of
microprocessor–based systems.
V
TRK
Output Voltage
This output uses the same type of output device as V
STBY
,
but is rated for 250 mA. The output is configured as a
tracking regulator of the standby output. By using the
standby output as a voltage reference, giving the user an
external programming lead (Adj lead), output voltages from
3.3 V to 20 V are easily realized. The programming is done
with a simple resistor divider, and following the formula:
VTRK
VSTBY
(1
R1 R2)
IAdj
R1
If another 3.3 V output is needed, simply connect the Adj
lead to the V
TRK
output lead.
C1*
0.1
μ
F
GND
CS8363
MCU
B+
V
IN
V
TRK
Adj
ENABLE
RESET
V
STBY
R3
V
DD
C2**
10
μ
F
ESR < 8.0
3.3 V, 100 mA
RESET
I/O
R2
R1
C3**
10
μ
F
ESR < 8.0
SW 5.0 V,
250 mA
GND
V
TRK
V
STBY
(1 + R1/R2)
For V
TRK
5.0 V, R1/R2
0.5
*C1 is required if regulator is located far from power supply filter.
**C2 and C3 are required for stability.
Figure 2. Test and Application Circuit, 3.3 V, 5.0 V Regulator
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