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參數(shù)資料
| 型號： | CSP1027 |
| 元件分類： | Codec |
| 英文描述： | CSP1027 Voice Band Codec for Cellular Handset and Modem Applications |
| 中文描述： | CSP1027語音頻帶編解碼器的蜂窩手機和調制解調器應用 |
| 文件頁數(shù)： | 33/64頁 |
| 文件大小： | 937K |
| 代理商： | CSP1027 |
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Lucent Technologies Inc.
Data Sheet
December 1999
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
33
7 Application Information
This section begins with application information for the
analog section, followed by power distribution, crystal
oscillator, and codec clock generation programming
examples.
7.1 Analog Information
The A/D input block is covered first, followed by the
D/A, and the microphone voltage regulator.
7.1.1 A/D in the Preamplifier Mode
Figure 28 on page 34 shows a typical telephone hand-
set application. The codec is shown with the preamp
mode (EIGS = V
SS
) selected and connected to a micro-
phone. The analog-to-digital conversion path begins
with an on-chip preamplifier front end having two
single-ended inputs. The preamp inputs are MICIN and
AUXIN. Selection of MICIN or AUXIN is made via the
INSEL field in the
cioc0
register (see Table 8 on page
27) and can be dynamically changed, as desired. The
electrical specifications for both inputs are the same.
An off-chip ac-coupling capacitor, Cin, is required
before each input. However, if either input is unused, it
may be left unconnected (floating). The input resis-
tance (Rin) to either MICIN or AUXIN is approximately
40 k
. The recommended value of Cin is 0.15 μF. This
creates a high-pass filter pole at approximately 26 Hz.
A larger capacitor value may be used if desired, in
order to allow lower frequencies to pass to the A/D con-
verter, but smaller capacitor values are not recom-
mended.
7.1.2 A/D in the External Input Gain Select Mode
The external input gain select (EIGS = V
DD
) is used
when the input range is set by the user (see Section
4.3 on page 13). The A/D input circuitry of Figure 28 on
page 34 is modified as shown in Figure 5 on page 7.
When EIGS = V
DD
, the following notes apply.
1. The recommended range of values for the feedback
resistor and capacitor are the following:
10 k
≤
Rfb
≤
45 k
and 150 pF
≤
Cfb
≤
680 pF.
Rin
2. The
impacts the absolute accuracy of the A/D path. A 1%
ratio error adds 86 mdB of absolute gain error.
external resistor ratio accuracy directly
3. The A/D input sampling switches have an effective
bandwidth on the order of 15 MHz. The amplifier
unity gain frequency is on the order of 3 MHz. High-
frequency noise in the 1 MHz to 50 MHz range that
couples to the AUXIN pin will be somewhat attenu-
ated by the amplifier output impedance, but a signifi-
cant portion will be sampled by the A/D and aliased
down to the baseband. Special care in circuit board
layout is required to keep noise sources from cou-
pling into the AUXIN or MICIN pins so that the noise
and distortion performance shown in Table 16 on
page 52 can be achieved.
The codec is not as sensitive to wideband noise
when the preamplifier is used (EIGS = V
SS
) because
the A/D inputs are driven from an on-chip low-pass
filter.
4. The external gain mode input circuitry of Figure 5 on
page 7 is an integrator with a great deal of loss. The
frequency response of Table 16 on page 52
assumes that the Rfb
×
Cfb corner frequency is
25 kHz so the 3 kHz droop is less than 65 dBm. Sim-
ilarly, the Cin
×
Rin corner frequency is set to 7 Hz.
These RC combinations create a bandpass anti-
aliasing filter with corner frequencies given by:
When selecting component values, verify that the
A/D frequency response will still meet the application
requirements.
7.1.3 D/A Analog Output
The CSP1027 D/A has two analog outputs, AOUTP
and AOUTN, capable of operating as two single-ended
drivers, or a single fully differential driver. The output
impedance of each is no more than 6
(12
if config-
ured as fully differential) over the dc to 4 kHz frequency
range.
The maximum open-circuit output levels are 2.1 Vp
(4.2 Vp-p) if fully differential, and one-half of these lev-
els if single-ended. These levels correspond to a full-
scale 16-bit two's complement PCM input into the D/A
converter, with the output gain setting (OGSEL) at
0 dB. For any given PCM input, the output levels will be
reduced by a voltage division of the D/A output and the
load impedance:
The driver linearity is only guaranteed for the single-
ended output load resistance (R
L
) of at least 1000
and the differential output load resistance (R
L
) of at
least 2000
.
---------
f
LO
2
π
Rin
×
Cin
×
--------------------------------------
f
HI
2
π
Rfb
×
Cfb
×
---------------------------------------
=
=
V
OUT
V
O
+
R
O
R
L
---------------------
×
=
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