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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01
User
’
s Manual U14260EJ3V1UD
Table 8-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins
(1) TI00n pin valid edge selected as capture trigger (CRC01n = 1, CRC00n = 1)
CR00n Capture Trigger
TI00n Pin Valid Edge
ES01n
ES00n
Falling edge
Rising edge
0
1
Rising edge
Falling edge
0
0
No capture operation
Both rising and falling edges
1
1
(2) TI01n pin valid edge selected as capture trigger (CRC01n = 0, CRC00n = 1)
CR00n Capture Trigger
TI01n Pin Valid Edge
ES11n
ES10n
Falling edge
Falling edge
0
0
Rising edge
Rising edge
0
1
Both rising and falling edges
Both rising and falling edges
1
1
Remarks 1.
Setting ES01n, ES00n = 1, 0 and ES11n, ES10n = 1, 0 is prohibited.
2.
ES01n, ES00n:
Bits 5 and 4 of prescaler mode register 0n (PRM0n)
ES11n, ES10n:
Bits 7 and 6 of prescaler mode register 0n (PRM0n)
CRC01n, CRC00n: Bits 1 and 0 of capture/compare control register 0n (CRC0n)
3.
n = 0, 1
Cautions 1. Set CR00n to a value other than 0000H in the clear & start mode entered on a match between
TM0n and CR00n. However, in the free-running mode and in the clear & start mode using
the valid edge of the TI00n pin, if CR00n is set to 0000H, an interrupt request (INTTM00n)
is generated when CR00n changes from 0000H to 0001H following overflow (FFFFH).
2. If the new value of CR00n is less than the value of 16-bit timer counter 0n (TM0n), TM0n
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR00n is less than the old value, therefore, the timer must be reset to be restarted after the
value of CR00n is changed.
3. When P70 is used as the input pin for the valid edge of TI000, it cannot be used as a timer
output (TO00). Moreover, when P70 is used as TO00, it cannot be used as the input pin for
the valid edge of TI000.
4. When P75 is used as the input pin for the valid edge of TI001, it cannot be used as a timer
output (TO01). Moreover, when P75 is used as TO01, it cannot be used as the input pin for
the valid edge of TI001.
5. When CR00n is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value). If count stop
input and capture trigger input conflict, the captured data is undefined.