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參數(shù)資料
| 型號： | CX72301-11 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Spur-Free, 1.0 GHz Dual Fractional-N Frequency Synthesizer |
| 中文描述： | 支線免費，1.0 GHz雙分?jǐn)?shù)N頻率合成器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | CX72301-11 |
DATA SHEET CX72301
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101090H Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 21, 2004
7
To achieve a desired F
frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum
divide ratio is 32, the reference frequency (F
) must be a maximum of 12.5 MHz. Choosing a reference
frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore:
Ninteger
= Fvco_aux
Fdiv_ref
=
400
8
=
50
The value to be programmed in the Auxiliary Divider Register is:
Nreg= Ninteger – 32
= 50 – 32
= 18 (decimal)
= 000010010(binary)
Summary:
·
Auxiliary Divide Register = 0 0001 0010
C1416
Figure 5. Integer-N Applications: Sample Calculation
In applications where the main synthesizer is in 10-bit mode, the
Main Dividend Register
holds the 10 bits of the dividend. The
registers that control the main synthesizer’s divide ratio are to be
loaded in the following order:
Main Divider Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
For the auxiliary synthesizer, the Auxiliary Dividend Register holds
the 10 bits of the dividend. The registers that control the auxiliary
synthesizer’s divide ratio are to be loaded in the following order:
Auxiliary Divider Register
Auxiliary Dividend Register (at which point the new divide ratio
takes effect)
NOTE
:
When in integer mode, the new divide ratios take effect
when the Main or Auxiliary Divider Register is loaded.
Direct Digital Modulation
The high fractionality and small step size of the CX72301 allow
the VCO to be tuned to practically any frequency in the VCO’s
operating range. This frequency tuning allows direct digital
modulation by programming the different desired frequencies at
precise instants. Typically, the channel frequency is selected
through the Main Divider and Dividend Register and the
instantaneous frequency offset from the carrier is entered through
the Modulation Data Register.
The Modulation Data Register can be accessed in three ways,
which are defined in the following subsections.
Normal Register Write
. A normal 16-bit serial interface write
occurs when CS is 16 clock cycles wide. The corresponding
16-bit modulation data is simultaneously presented to the Data
pin. The content of the Modulation Data Register is passed to the
modulation unit at the next falling edge of the divided main VCO
frequency (
F
pd_main
).
Short CS Through Data Pin (No Address Bits Required)
. A
shortened serial interface write occurs when CS is 16 clock
cycles wide. The corresponding modulation data (2 to 12 bits) is
simultaneously presented to the Data pin. The Data pin is the
default pin used to enter modulation data directly into the
Modulation Data Register with shortened CS strobes. This method
of data entry eliminates the register address overhead on the
serial interface. All serial interface bits are re-synchronized
internally at the reference oscillator frequency. The content of the
Modulation Data Register is passed to the modulation unit at the
next falling edge of the divided main VCO frequency (
F
pd_main
).
Short CS Through Mod_in Pin (No Address Bits Required)
. A
shortened serial interface write where CS is from 2 to 12 clock
cycles wide and modulation data (2 to 12 bits) is presented on the
Mod_in pin. The Mod_in pin is the alternate pin used to enter
modulation data directly into the Modulation Data Register with
shortened CS strobes. This mode is selected through the
Modulation Control Register. This method of data entry also
eliminates the register address overhead on the serial interface
and allows a different device than the one controlling the channel
selection to enter the modulation data (e.g., a microcontroller for
channel selection and a digital signal processor for modulation
data).
All serial interface bits are re-synchronized internally at the
reference oscillator frequency and the content of the Modulation
Data Register is passed to the modulation unit at the next falling
edge of the divided main VCO frequency (
F
pd_main
).
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