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參數(shù)資料
| 型號： | CX72301 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Spur-Free, 1.0 GHz Dual Fractional-N Frequency Synthesizer |
| 中文描述： | 支線免費，1.0 GHz雙分?jǐn)?shù)N頻率合成器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | CX72301 |
DATA SHEET CX72301
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
July 21, 2004 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 101090H
6
Case 2
: To achieve a desired F
frequency of 917.7786 MHz using a crystal frequency of 19.2 MHz with operation
of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (F
div_ref
) is 25 MHz, the crystal
frequency does not require the internal division to be greater than 1, which makes F
div_ref
= 19.2 MHz. Therefore:
Nfractional = Fvco_main
Fdiv_ref
= 917.7786
19.2
= 47.80097
The value to be programmed in the Main Divider Register is:
Nreg= Round[Nfractional] – 32
= Round[47.80097] – 32
= 48 – 32
= 16 (decimal)
= 000010000(binary)
With the modulator in 10-bit mode, the value to be programmed in the Main Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[1024 × (47.80097 – 16 – 32)]
= Round[1024 × (– 0.1990312)]
= Round[– 203.808]
= 204 (decimal)
= 1100110100 (binary)
where 11 0011 0100 is loaded in the MSB of the Main Dividend Register.
Summary:
·
Main Divider Register = 0 0001 0000
·
Main Dividend MSB Register = 11 0011 0100
·
The resulting main VCO frequency is 917.775 MHz
·
Step size is 18.75 kHz
Note: The frequency step size for this case is 19.2 MHz divided by 2
10
, giving 18.75 kHz.
C1415
Figure 4. Fractional-N Applications: Sample Calculation (2 of 2)
Integer-N Applications
. The desired division ratio for the main or
auxiliary synthesizer is given by:
N
integer
F
F
div
_
ref
---------------------------
=
where
N
integer
is an integer number from 32 to 543 for both the
main and auxiliary synthesizers.
The value to be programmed in the Main or Auxiliary Divider
Register is given by the following equation:
N
reg
F
integer
32
–
=
When in integer mode, allowed values for
N
reg
are from 0 to 511
for both the main and auxiliary synthesizers.
NOTE
:
As with all integer-N synthesizers, the minimum step size
is related to the crystal frequency and reference
frequency division ratio.
A sample calculation for an integer-N application is provided in
Figure 5.
Register Loading Order
. In applications where the main
synthesizer is in 18-bit mode, the Main Dividend MSB Register
holds the 10 MSBs of the dividend and the Main Dividend LSB
Register holds the
8 LSBs of the dividend. The registers that
control the main synthesizer’s divide ratio are to be loaded in the
following order:
Main Divider Register
Main Dividend LSB Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
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