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參數(shù)資料
| 型號： | CX74038-21 |
| 廠商： | SKYWORKS SOLUTIONS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PDSO20 |
| 封裝： | 6.5 X 4.4 MM, 1 MM HEIGHT, TSSOP-20 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 123K |
| 代理商： | CX74038-21 |
DATA SHEET CX74038 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101075J Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice August 29, 2005
3
DAT
CLK
LE
tDSU
tDHD
tCKH
tCLE
tLEW
tLEC
tCKL
C1457
Figure 3. CX74038 Serial Data Input Timing Diagram (MSB First)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
0
1
SP2
EN
1
0
SP1
SC1
PS
ME
1
FN
IF
RF
N1 DIVIDER
R1 DIVIDER
N2 DIVIDER
0
SC2
LD
R2 DIVIDER
D14
D15
D16
D17
D18
D19
D20
D21
LSB
MSB
C1456
Figure 4. CX74038 Serial Data Word Format
Registers
The CX74038 includes four 22-bit registers that can be
programmed independently in any order. Bits D0 and D1
represent the register addresses. For more information on
registers, addresses, and format, refer to the Synthesizer Register
Programming section of this document.
A dithering disable function is accessible via word 00, data bits
21 and 20. When the RF synthesizer is programmed for fractional
divide values, these bits should be programmed to 1 0 (dithering
enable). However, when the RF synthesizer is programmed to
output a frequency which is a whole integer multiple of the
comparison frequency, the synthesizer should be programmed for
dithering disabled (bits set to 11). This improves the phase noise
when operating on integer-N boundaries. These data bits must be
programmed after power-up, otherwise erroneous device
operation may occur. Refer to the Synthesizer Register
Programming section of this document for bit definitions.
Voltage Controlled Oscillator (VCO) Prescalers
The VCO prescalers, P/P+1 and Q/Q+1, provide low noise signal
conditioning of the VCO signals. They translate from an off-chip,
single-ended or differential signal to an on-chip differential signal.
By changing the PS bit, the RF synthesizer has the option to use
either the 8/9 or the 16/17 prescaler depending on the desired
operational frequency. The maximum frequency is 2.6 GHz for the
16/17 prescaler and 1.4 GHz for the 8/9 prescaler. The IF
synthesizer has a fixed 16/17 prescaler with a maximum
frequency of 800 MHz.
RF and IF Dividers
The CX74038 provides programmable dividers that control the
prescaler and supply the divided VCO signals to the charge pump
phase detectors. Programmable ratios on the RF fractional-N
synthesizer ranging from 256 to 212 are possible with the 16/17
prescaler, and from 64 to 211 with the 8/9 prescaler. The IF
integer-N synthesizer has a programmable divide ratio ranging
from 256 to 217.
Reference Frequency Dividers
The reference signal can be divided by a ratio of 1 to 7 for the RF
reference divider (R1) and from 1 to 8192 for the IF reference
divider (R2). The input frequency for the reference signal can be
as high as 50 MHz.
Phase Detectors and Charge Pumps
The CX74038 uses a separate charge pump phase detector for
each synthesizer. The IF and RF Phase/Frequency Detector (PFD)
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