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參數(shù)資料
| 型號： | CXA1352AS |
| 廠商： | Sony Corporation |
| 英文描述： | 2-channel 5 Elements Graphic Equalizer IC |
| 中文描述： | 2通道5元素的圖形均衡器集成電路 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 216K |
| 代理商： | CXA1352AS |
—10—
CXA1352AS
Here, using
ω
o and Q we can express BPF transmittance H (s) as
Z (s) =
Q
s+
1
+
ω
o Q
Gm1 s
ω
o Gm1
Gm1
This formula shows that this system and the aforementioned LCR circuit have equivalent impedance
characteristics on Z (s).
Then, regarding Gm as the maximum value of Gm1 and Gm2, the operation can be observed as follows.
Maximum cut occurs when Gm1=Gm and Gm2=0. At that time we have transmittance T (s) as
ω
o
s +
ω
o
2
Q
(1+R Gm)
ω
o
2
Q
T (s) =
Z (s)
Z (s) +R
=
This is equal to the frequency characteristics of the conventional graphic equalizer at cut.
Also, maximum boost occurs when Gm1=0 and Gm2=Gm. At that time we have transmittance T (s) as
(1+R Gm)
ω
o
2
Q
T (s) =
Z (s) +R
Z (s)
=
This is equal to the frequency characteristics of the conventional graphic equalizer at boost.
We can then deduce that, as far as the operation is concerned the graphic equalizer on this IC and the
conventional graphic equalizer are equal, even when the system differs. The merit in using this IC’s system
rests with the fact that monolithic filter technology realizes a graphic equalizer without external parts.
The structure of the actual graphic equalizer, including BPF, is shown on Fig. 4.
Fig. 4
H (s) =
ω
o
Q
ω
o
Q
s
s
2
+
s +
ω
o
2
s
2
+
s
2
+
s+
ω
o
2
s
2
+
ω
o
Q
s +
ω
o
2
s
2
+
s+
ω
o
2
R2
30k
SUM
V
O
Gm4
Gm3
Gm1
I CUT
I BOOST
GND
GND
GND
GND
GND
C2
C1
C3
Gm2
VI
V
I
1
1
R1
30k
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