參數(shù)資料
型號(hào)： CXA1854AR
廠商： Sony Corporation
元件分類： 外設(shè)及接口
英文描述： Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
中文描述： 電可擦除可編程邏輯器件
文件頁(yè)數(shù)： 24/45頁(yè)
文件大小： 1348K
代理商： CXA1854AR
– 24 –
CXA1854AR
Description of Operation
The CXA1854AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using BiCMOS technology. This section describes these functions and
their mutual relationship.
1) Description of the overall configuration
RGB decoder
EXT-R
EXT-G
EXT-B
Y
SYNC
C
R-Y
B-Y
CXA1854AR
ENB
CLR
VST1
VCK2
VCK1
HST1
HCK2
HCK1
FRP
R OUT
G OUT
B OUT
R
G
B
SYNC
BLK
3.58MHz
or 4.43MHz
R
C
RGB driver
TG
VCO
Corresponding LCD panels
LCX009AK/AKB
1.8cm 180K dots
LCX005BK/BKB
1.4cm 113K dots
2) Description of RGB decoder block operation
Input mode switching
Signal input: Composite input, Y/C input and Y/color difference input switching is supported by Pin 8
(MODE2).
During composite input:
The composite signal is input to Pins 1, 2 and 62.
During Y/C input:
The Y signal is input to Pins 1 and 2, and the C signal to Pin 62.
During Y/color difference input: The Y signal is input to Pins 1 and 2, the R-Y signal to Pin 50, and the B-Y
signal to Pin 49.
(Chroma signal input (delay line output) is also used during PAL, but is
switched with the MODE1 setting.)
Recommended input signal voltages for each mode are shown in the Pin Description table. The Y signal
enters the TRAP circuit in composite mode, but through operation is performed in all other modes. Also, the
picture center frequency is set separately for composite input and Y/C input. (See the AC Characteristics
tables.)
NTSC/PAL switching
NTSC and PAL (DPAL using an external delay line and SPAL) are switched by MODE1.
The built-in TRAP and BPF center frequencies are switched automatically according to the external crystal.
The center frequency is stabilized by the APC operation.
The R-Y demodulation detective axis is set internally to 90° during SPAL/DPAL. However, optimally adjust
the demodulation phase axis with the HUE adjustment pin.
Video AGC/ACC circuit
Different AGC characteristics are obtained depending on the APL level of the luminance signal. The gain for
the luminance signal is adjusted with the average value. The sync amplitude of the burst signal output is
detected and used to adjust the ACC amplifier gain.
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