參數(shù)資料
型號(hào)： CXA3266Q
元件分類： PLL合成/DDS/VCOs
英文描述： PHASE LOCKED LOOP, 0.12 MHz, PQFP48
封裝： PLASTIC, QFP-48
文件頁(yè)數(shù)： 47/62頁(yè)
文件大?。?/td> 929K
代理商： CXA3266Q
CXA3266Q
- 51 -
CXA3266Q and Sony ADC (Straight Mode) Timing : 100MHz specification
The CXA3266Q and CXA3276Q/CXA3286R timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
For the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. clock output from CXA3266Q
The setup time is T – 5.2ns and the hold time is 0.3ns. (These timings also include combinations of three
A/D converters from different lots, and are defined for all operating temperatures and all operating supply
voltages. See the CXA3276Q/CXA3286R data sheets for a detailed description.)
For the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3266Q vs. A/D converter clock output
The setup time is T – 3.0ns and the hold time is 1.0ns.
T
3.5ns min.
CLK (PECL)
out
CLK (TTL)
out
DSYNC (TTL)
out
DATA (TTL)
out
CXA3276Q
CXA3286R
CXA3266Q
7.0ns max.
1.8 to 3.2ns
1.0 to 3.0ns
1.0ns
Thold min.
0.3ns
Thold min.
Tsetup min.
T - 3.0ns
Tsetup min.
T - 5.2ns
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