- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378470 > CXB1586AR (Sony Corporation) 10 Bit 1.0625 Gbaud Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | CXB1586AR |
| 廠商： | Sony Corporation |
| 英文描述： | 10 Bit 1.0625 Gbaud Transceiver |
| 中文描述： | 10位1.0625 Gbaud收發(fā)器 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 307K |
| 代理商： | CXB1586AR |
—6—
CXB1586AR
Pin description
Symbol
VEET
TX0-9
VCCG
VEEP_TX
LPF_TX0
LPF_TX1
VCCP_TX
LBEN
VEEG
REFCLK
BYTSYNCEN
TEST
LCKREF
VCCT
RBC1
RBC0
RX0-9
BYTSYNC
LPF_RX0
LPF_RX1
VCCP_RX
VEEP_RX
Pin No.
1, 14, 32,
33, 46
2-4, 6-9,
11-13
5, 10, 20,
23, 28, 55,
57, 59
15
16
17
18
19
21, 25,
56, 58
22
24
26
27
29, 37, 42
30
31
34-36,
38-41,
43-45
47
48
49
50
51
Type
PS
I_TTL
PS
PS
EX
PS
I_TTL
PS
I_TTL
I_TTL
I_TTL
I_TTL
PS
O_TTL
O_TTL
O_TTL
EX
PS
PS
Equivalent
circuit
—
(a)
—
—
(e)
—
(a)
—
(a)
(a)
(a)
(a)
—
(b)
(b)
(b)
(e)
—
—
Description
Ground for TTL output : Normally 0 V.
Parallel transmit data inputs to be serialized.
TX0 is serialized first and TX9 is last.
Power supply for internal logic gates :
Normally 3.3 V.
Ground for TX PLL : Normally 0 V.
Connect to external loop filter of TX PLL. Connect a
capacitor (0.01 μF) between LPF_TX0 and LPF_TX1.
Power supply for TX PLL : Normally 3.3 V.
Loop back enable : When high, TX serializer output
internally connects to RX deserializer input,
SDOUT/SDOUT
is held low/high, and SDIN/SDIN
is
disabled. When low, SDOUT/SDOUT
and
SDIN/SDIN
are enabled.
Power supply for internal logic gates :
Normally 0 V.
Reference clock for PLL and transmit byte clock
(106.25 MHz). Supplied by the host system.
Byte synchronization enable : When high, the positive
comma character (0011111) detection circuit is
enabled to establish byte synchronization (see Timing
Chart).
Test pin : Normally 3.3 V or open.
Lock to reference clock : An active low input.
LCKREF
forces the PLL lock to the REFCLK supplied
by the host system.
Power supply for TTL output : Normally 3.3 V.
Receive byte clocks recovered from the serial data
(53.125 MHz). These clocks are 180 degrees out of
phase, and RX0-9 are alternatively clocked on the
rising edge of these clocks (see Timing Chart)
Parallel receive data output :
RX0 is received first and RX9 is last.
Byte synchronization indicator : High when a positive
comma character is detected (see Timing Chart)
Connect to external loop filter of RX PLL. Connect a
capacitor (0.01 μF) between LPF_RX0 and LPF_RX1.
Power supply for RX PLL : Normally 3.3 V.
Ground for RX PLL : Normally 0 V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXB1590Q | SDH 8-Bit 622 Mbps Transceiver(8位、622Mbps同步數(shù)字系列數(shù)據(jù)（SDH）收發(fā)器) |
| CXB1595AN | Fibre Channel Repeater(光纖通道中繼器) |
| CXB1596AR | 10-Bit Transceiver With A Built-In PLL For Fibre Channel And Gigabit Ethernet(10位收發(fā)器（內(nèi)置鎖相環(huán)電路，用于光纖通道和千兆位以態(tài)網(wǎng)）) |
| CXB1810FN | Post Amplifier for Optical Fiber Communication Receiver |
| CXD101-106Q | C-MOS DIGITAL DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXB1586R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
| CXB1589R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| CXB1590Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| CXB1595AN | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Fibre Channel Repeater |
| CXB1596AR | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:10-bit Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。