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參數(shù)資料
| 型號： | CXB1590Q |
| 廠商： | Sony Corporation |
| 英文描述： | SDH 8-Bit 622 Mbps Transceiver(8位、622Mbps同步數(shù)字系列數(shù)據(jù)（SDH）收發(fā)器) |
| 中文描述： | SDH的8位622 Mbps的收發(fā)器（8位，速率達622Mbps同步數(shù)字系列數(shù)據(jù)（SDH）的收發(fā)器） |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | CXB1590Q |
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CXB1590Q
I/O Timing
1. Transmitter
Transmitting parallel clock (TPCLK) is 77.76 MHz clock made from transmitting clock by the divider. It
provides timing of TPD<7..0>.
Transmitting parallel data (TPD<7..0>) are the bus of 77.76 Mbps Tx byte stream. TPD is converted into
output-serial-data by P/S converter.
Timing between TPCLK and TPD<7..0> is able to adjust by another inputs (TPDLC
, DLY0, DLY1). This
timing has 5 kinds ; DLY0, DLY1, DLY3, DLY5, DLY7.
Timing of TPD for TPCLK (set up, hold time) is shown in Fig. 5 and Table 11.
FIg. 5 Transmitter Section Timing
Table 11 Timing Mode Selection Table
Ts_TPD
Th_TPD
Valid
TPCLK
77.76MHz
TTL-output
Vth=1.4V
TPD
77.76Mbps
TTL-input
Vth=1.4V
TPDLC
1
0
0
0
0
DLY0
X
0
1
0
1
DLY1
X
0
0
1
1
timing
DLY0
DLY1
DLY3
DLY5
DLY7
Ts_TPD (nsec)
3.6
5.4
8.3
11.6
14.5
Th_TPD (nsec)
0.0
–1.8
–4.8
–8.0
–10.9
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