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CXD1196AR
2.1.4
DECODER CONTROL (DECCTL) Register
AUTOCI (Auto Coding Information)
‘H’
:
To perform ADPCM playback according to the coding information from the drive. In this
case, the CI register need not be set.
‘L’
:
To perform ADPCM playback according to the value of the CI register.
RESERVED
Should be kept at ‘L’ at all times.
MODESEL (Mode Select)
FORMSEL (Form Select)
When AUTODIST = ‘L’, the sector is corrected as the following MODE and FORM.
Bit7
Bit6
Bit5
Bit4
Bit3
AUTODIST (Auto Distinction)
‘H’
:
Errors are corrected according to the MODE byte and FORM bit read from the drive.
‘L’
:
Errors are corrected according to bit 5 MODESEL and bit4 FORMSEL.
Bit2-0
:
DECMD 2-0 (Decoder Mode 2-0)
These bits are set at ‘L’ when the CDDA bit (bit3) of the CHPCTL register is ‘H’.
2.1.5
Interrupt Mask (INTMSK) Register
When the individual bits of this register are set at ‘H’, an interrupt request from the CXD1196AR to the CPU
is enabled in response to the corresponding interrupt status. (That is, when the interrupt status is created,
the INT pin is made active.) The value of the individual bits of the register does not affect the
corresponding interrupt status.
Bit7
ADPEND (ADPCM End)
When this chip has completed the ADPCM decode for a sector, if the ADPCM decode for the next
sector is not enabled, the ADPEND status is created.
DECTOUT (Decoder Time Out)
If no SYNC mark is detected during a period of 3 sectors (40.6 ms in normal speed playback mode)
after the DECODER has been set in the monitor only, and real time correction modes, the DECTOUT
status is created.
DMACMP (DMA Complete)
When DMA is ended by DMAXFRC, the DMACMP status is created.
Bit6
Bit5
MODESEL
‘L’
‘H’
‘H’
FORMSEL
‘L’
‘L’
‘L’
MODE1
MODE2, FORM1
MODE2, FORM2
DECMD2
‘L’
‘L’
‘H’
‘H’
‘H’
‘H’
DECMD1
‘L’
‘H’
‘L’
‘L’
‘H’
‘H’
DECMD0
‘X’
‘X’
‘L’
‘H’
‘L’
‘H’
Decoder disable
Monitor only mode
Write only mode
Real time correction mode
Repeat correction mode
Inhibit