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CXD1947Q
IEEE1394 LINK Layer / PCI Bridge LSI
Overview
The CXD1947Q is a single-chip implementation of the
link layer protocol of the 1394 Serial Bus, with additional
features to support the transaction and bus management
layers.
The CXD1947Q includes a PCI bus interface and mul-
tiple DMA engines to enable high performance bus
transfers.
Features
1394 Link Layer/PCI Bridge
Conforms to IEEE1394 high speed Serial Bus
Supports 100Mb/s and 200Mb/s 1394 bus speeds
Conforms to PCI version 2.1 specification
Supports 6 independent programmable DMA channels
—
Asynchronous transmit (1)
—
Asynchronous receive (1)
—
Isochronous transmit (2)
—
Isochronous receive (2)
Three 128-word-deep FIFOs
—
Asynchronous transmit
—
Isochronous transmit
—
Receive
–1–
10/18/96
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or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
160 pin QFP
PRELIMINARY
Includes interfaces to
—
1394 PHY interface (CXD1944 or equivalent)
—
ROM (64K x 8)
—
Silicon Serial ROM
Supports big and little Endian data formats
Device Structure
Silicon gate CMOS IC
Recommended Operating Conditions
Supply voltage
Operating temperature range Topr
V
DD
3.0 to 3.6
–20 to +75
V
°C
Block Diagram
PCI INF
PCI BUS
MBIU
ITDMA
ATDMA
RDMA
IRDMA
ALIGN
ALIGN
ALIGN
SSN INF
ROM INF
CNTL REG
ITF
ATF
RF
LI
CORE
PHY
MBIU:
ITDMA: Isochronous Transmit DMA
ATDMA: Asynchronous Transmit DMA
RDMA: Receive DMA
IRDMA: Isochronous Receive DMA
Master Bus Interface
ALIGN:
ITF:
ATF:
RF:
SSN INF:
Data Aligner
Isochronous Transmit FIFO
Asynchronous Transmit FIFO
Receive FIFO
Silicon Serial Number
PHY:
Link Layer/Physical Layer
1394 Interface
ROM Interface
ROM INF:
CNTL REG: Control Registers