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參數(shù)資料
| 型號： | CXD2314R |
| 廠商： | Sony Corporation |
| 英文描述： | 9-bit 20MSPS Video A/D Converter |
| 中文描述： | 9位20MSPS視頻A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 247K |
| 代理商： | CXD2314R |
– 11 –
CXD2314R
1. Calibration Function
In order to achieve superior linearity, the CXD2312R has a built-in calibration circuit and a calibration pulse
auto generation circuit which is used to execute a calibration circuit. Fig. 1 shows a block diagram of the
calibration pulse generation circuit.
AV
DD
OUT
14 bit
Counter
24 bit
Counter
CLR
CLR
CO
CO
CLR
SEL
CAL
D Q
16
1
CLK
AV
DD
AV
SS
VRT
VRB
RESET
CE
Sence
Amp 1
Sence
Amp 2
Fig. 1. Calibration Pulse Generation Circuit
(1) Startup Calibration Function
Over 600 calibration pulses are needed to complete the initial calibration process when the power is first
supplied to the IC. The startup calibration function automatically generates these pulses internally and
completes the initial calibration process.
The following five conditions must be satisfied to initiate the
startup calibration function.
a) The voltage between AV
DD
and AV
SS
is approximately
2.5V or more.
b) The voltage between VRT and VRB is approximately 1V
or more.
c) The RESET pin (Pin 15) must is high.
d) The CE pin (Pin 24) must is low.
e) Condition b is met after condition a.
Once all five of these conditions have been met, the calibration
pulses are generated. The pulses are generated by counting 16
main clock cycles on a 14-bit counter and closing the gate when
the carry-out occurs. Therefore, the time required for startup
calibration after the above five conditions have been met is
determined by the following formula:
Startup calibration time = main clock cycle
×
16
×
16,384
For example, if the main clock frequency is 14.3MHz, the time required for startup calibration is 18ms.
When RESET = High and CE = Low
AV
DD
VRT
VRB
1V
[V]
5
2.5
0
[ t ]
Sence Amp 1
Sence Amp 2
CLR
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