參數(shù)資料
型號(hào): CXD2443Q
廠商: Sony Corporation
英文描述: Timing Generator for LCD Panels
中文描述: 時(shí)序發(fā)生器的液晶面板
文件頁數(shù): 17/57頁
文件大?。?/td> 8722K
代理商: CXD2443Q
– 17 –
CXD2443Q
XCLR pin
The CXD2443Q should be forcibly reset during power on in order to initialize the serial transfer block and other
internal circuits.
Serial transfer operation
1. Control method
The CXD2443Q operation timing is controlled by serial data.
The control data is comprised of an 8-bit address and 8-bit data, and the individual data is fetched at the rise
of SCLK. This fetching operation starts from the fall of SCTR and is completed at the next rise of SCTR.
Serial transfer timing
2. Control data
When using the CXD2443Q, set the control data corresponding to each signal source according to the formats
in the table below.
D15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
HP8
VM7J
VM7K
HP7
VM6J
VM6K
HP6
VM5J
VM5K
TEST4
HP5
VM4J
VM4K
TEST3
HP4
VP4
SLSH4
VM3J
VM3K
SL3B
SNSL
HP3
VP3
SLSH3
VM2J
VM2K
VPOL
XHD
HP2
VP2
SLSH2
CP2
PCGW2
VM9J
VM1J
VM9K
VM1K
TEST1
MA
DWN
HPOL
SLVWB
XWID
HP1
VP1
SLSH1
CP1
PCGW1
VM8J
VM0J
VM8K
VM0K
SLBA
TEST2
RGT
SLFR
SLEG
NT-PAL
(A) H-POSITION
(B) V-POSITION
(C) SH-POSITION
(D) XCLP-POSITION
(E) PCG-POSITION
(F) VWA-POSITION
(VWA pulse)
(G) Double-speed
setting
(H) Double-speed
PAL pulse eliminate
(I) Right/left and/or
up/down inversion
(J) Various settings
(K) Mode settings
D14D13
D12
D11D10
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
Note)
1. Set "High" as the TEST1, TEST2, TEST3 and TEST4 data.
2. "—" indicates not set.
Address
Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDAT
SCLK
SCTR
Address
Data
Function
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