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    參數(shù)資料
    型號(hào): CXD2458AR
    廠商: Sony Corporation
    英文描述: Timing Generator for Color LCD Panels
    中文描述: 時(shí)序發(fā)生器彩色液晶面板
    文件頁數(shù): 12/56頁
    文件大?。?/td> 1555K
    代理商: CXD2458AR
    – 12 –
    CXD2458AR
    16:9 (WIDE) Display Mode
    Setting the WIDE pin to H shifts the unit to WIDE display mode. In this mode, the aspect ratio is converted
    through pulse eliminator processing, allowing 16:9 quasi-WIDE display.
    Vertical pulse eliminator scanning of 1/4 (NTSC) and 2/6 (PAL) for the LCX005BK/BKB and LCX009AK/AKB,
    and 1/4 (NTSC) and 10/28 (PAL) for the LCX024AK and LCX027AK is performed, and the video signal is
    compressed in the display area compared to 4:3 display to achieve 16:9 (WIDE) display. In addition, in areas
    outside the display area, vertical high-speed scanning is performed and black signals are written to the black
    display area in the upper 28 lines and the lower 27 or 28 lines. During this period, the FRP and HST output
    cycles are also changed, and EN and CLR are not output. In addition, the SBLK output, which is the black
    signal generation timing pulse, and the LCX024AK/LCX027AK black display area control signal BLK are both
    H.
    (For example, black display in the panel is permitted by connecting the SBLK output to the external RGB input
    pin of the CXA1785AR.)
    See the Timing Charts for details.
    4:3 display
    28 LINES
    (28 LINES)
    218 LINES
    (225 LINES)
    Vertical pulse eliminator scanning
    Vertical high speed scanning
    16:9 display
    AAAA
    AAA
    AAAA
    Black display area
    AAA
    Display area
    163 LINES
    (169 LINES)
    27 LINES
    (28 LINES)
    AAA
    AAA
    Display area
    AAAA
    AAAA
    Black display area
    Numbers in parentheses are for the LCX009AK/AKB and LCX027AK.
    Note)
    When the no signal status occurs during 16:9 (WIDE) display mode, 4:3 display mode results.
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