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參數(shù)資料
| 型號： | CXD2463 |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Controller for CCD Camera |
| 中文描述： | 時序控制器CCD相機(jī) |
| 文件頁數(shù)： | 14/37頁 |
| 文件大?。?/td> | 414K |
| 代理商： | CXD2463 |
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CXD2463R
3) VReset + HPLL (VD and HD Inputs) Mode
When the HD cycle clock is externally input to EHD/SYNC (Pin 38) and the V cycle clock is externally input to
the EVD (Pin 37), the CXD2463R sync signal is output as shown below based on the phase difference
between these signals.
Similar to Line-Lock mode, the result of comparing the phase of the falling edges of the HD cycle clock input to
Pin 38 and the CXD2463R internal HD is output from COMP (Pin 39). The PLL is applied using this signal.
Similar to Line-Lock mode, the polarity of the COMP (Pin 39) output is compatible with the active filter. The
phase of the HD falling edge can be shifted up to ±1/4H with respect to the falling edge of the master VD (EXT-
VD).
EIA/ODD
(1) EXT-VD and EXT-HD have the same phase.
1/4H1/4H
EXT-VD
(Pin 37 input)
EXT-HD
(Pin 38 input)
VD
(Pin 35 output)
HD
(Pin 36 output)
SYNC
(Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
(3) EXT-VD and EXT-HD have the –1/4H to the same phase.
EXT-VD
EXT-HD
VD
HD
SYNC
相關(guān)PDF資料 |
PDF描述 |
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| CXD2463R | Timing Controller for CCD Camera |
| CXD2480R | Timing Controller IC with Built-in CCD Driver |
| CXD2510Q | CD Digital Signal Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2463R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Controller for CCD Camera |
| CXD2464R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for LCD Panels |
| CXD2467AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Digital Signal Driver/Timing Generator |
| CXD2467Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Digital Signal Driver/Timing Generator |
| CXD2470R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Frame Readout CCD Image Sensor |
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