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參數(shù)資料
| 型號(hào)： | CXD2586R |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor With Built-In Digital Servo and DAC(CD數(shù)字信號(hào)處理器（內(nèi)置數(shù)字伺服系統(tǒng)和D/A轉(zhuǎn)換器）) |
| 中文描述： | CD數(shù)字信號(hào)處理器），配有數(shù)字式伺服和DAC（光盤數(shù)字信號(hào)處理器（內(nèi)置數(shù)字伺服系統(tǒng)和的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/127頁 |
| 文件大?。?/td> | 1694K |
| 代理商： | CXD2586R |
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CXD2586R/-1
Contents
[1] CPU Interface
§1-1.
§1-2.
§1-3.
§1-4.
CPU Interface Timing ...................................................................................................................... 15
CPU Interface Command Table ...................................................................................................... 15
CPU Command Presets .................................................................................................................. 25
Description of SENS Signals ........................................................................................................... 30
[2] Subcode Interface
§2-1.
P to W Subcode Readout ................................................................................................................ 57
§2-2.
80-bit Sub Q Readout ...................................................................................................................... 57
[3] Description of Modes
§3-1.
CLV-N Mode .................................................................................................................................... 63
§3-2.
CLV-W Mode ................................................................................................................................... 63
§3-3.
CAV-W Mode ................................................................................................................................... 63
[4] Description of Other Functions
§4-1.
Channel Clock Regeneration by the Digital PLL Circuit .................................................................. 65
§4-2.
Frame Sync Protection .................................................................................................................... 67
§4-3.
Error Correction ............................................................................................................................... 67
§4-4.
DA Interface ..................................................................................................................................... 68
§4-5.
Digital Out ........................................................................................................................................ 71
§4-6.
Servo Auto Sequence ...................................................................................................................... 72
§4-7.
Digital CLV ....................................................................................................................................... 80
§4-8.
Playback Speed ............................................................................................................................... 81
§4-9.
DAC Block Playback Speed ............................................................................................................ 82
§4-10. DAC Block Input Timing .................................................................................................................. 82
§4-11. CXD2586R/-1 Clock System ........................................................................................................... 84
[5] Description of Servo Signal Processing-System Functions and Commands
§5-1.
General Description of the Servo Signal Processing System .......................................................... 85
§5-2.
Digital Servo Block Master Clock (MCK) ......................................................................................... 86
§5-3.
AVRG Measurement and Compensation ........................................................................................ 86
§5-4.
E:F Balance Adjustment Function ................................................................................................... 88
§5-5.
FCS Bias Adjustment Function ........................................................................................................ 88
§5-6.
AGCNTL Function ........................................................................................................................... 90
§5-7.
FCS Servo and FCS Search ........................................................................................................... 92
§5-8.
TRK and SLD Servo Control ........................................................................................................... 93
§5-9.
MIRR and DFCT Signal Generation ................................................................................................ 94
§5-10. DFCT Countermeasure Circuit ........................................................................................................ 95
§5-11. Anti-Shock Circuit ............................................................................................................................ 95
§5-12. Brake Circuit .................................................................................................................................... 96
§5-13. COUT Signal ................................................................................................................................... 97
§5-14. Serial Readout Circuit ...................................................................................................................... 97
§5-15. Writing the Coefficient RAM ............................................................................................................ 98
§5-16. PWM Output .................................................................................................................................... 98
§5-17. DIRC Input Pin ............................................................................................................................... 100
§5-18. Servo Status Changes Produced by the LOCK Signal .................................................................. 101
§5-19. Description of Commands and Data Sets ..................................................................................... 101
§5-20. List of Servo Filter Coefficients ...................................................................................................... 113
§5-21. FILTER Composition ..................................................................................................................... 115
§5-22. TRACKING and FOCUS Frequency Response ............................................................................ 122
[6] Application Circuit
§6-1.
Application Circuit .......................................................................................................................... 123
Explanation of abbreviations
AVRG:
AGCNTL: Automatic gain control
FCS:
Focus
TRK:
Tracking
SLD:
Sled
DFCT:
Defect
Average
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PDF描述 |
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| CXD2586R-1 | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2587 | RESISTOR,MIL-PRF-39007/9 |
| CXD2587Q | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2588Q | RESISTOR,MIL-PRF-39007/9 |
| CXD2588R | CD Digital Signal Processor with Built-in Digital Servo and DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2586R/-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD-Player Processor/Controller |
| CXD2586R-1 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2587 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2587Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2588Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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