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參數(shù)資料
| 型號： | CXD2931R |
| 廠商： | Sony Corporation |
| 英文描述： | 1 Chip GPS LSI(單片全球定位系統(tǒng)（GPS）大規(guī)模集成電路LSI) |
| 中文描述： | 1全球定位系統(tǒng)大規(guī)模集成電路芯片（單片全球定位系統(tǒng)（GPS）的大規(guī)模集成電路LSI）的 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 216K |
| 代理商： | CXD2931R |
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CXD2931R
Battery Backup Mode
The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset
goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clock
are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and
the registers are initialized.
Battery backup mode is canceled by setting power-on reset to high.
Normal outputs
TXD0 to 2, OTCXO, HOLDA
Inputs
RXD0 to 2, IF0,
HOLD, NMI, PMI
Tri-state outputs
IODBK, RUN, CLKOUT
Hi-Z
Hi-Z
Fixed low
Fixed low
Fixed low
Fixed low
10 clocks
100ms or more
PWRST
Power-on reset
EXRS
Timer clocks
CCKI, CCKO
Other clocks
TCXO, XTCXO, CLKI, CLKO
Tri-state outputs
ICS0, ICS1, IADR[18:1],
IRD, IWR, DRD, DWR, XCS0
Bidirectional
SINT, IB[15:0], DCS0 to 5,
DADR[15:0], DB[7:0], PORT[22:0]
(Input)
(Outut)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD2951GA-2 | Single Chip GPS LSI |
| CXD3000R | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD3005R | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD3008Q | CD Digital Signal Processor with Built-in Digital Servo |
| CXD3009Q | CD Digital Signal Processor(CD數(shù)字信號處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2931R-9 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:1 chip GPS LSI |
| CXD2931R-9/GA-9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 chip GPS LSI |
| CXD2932AGA-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS Base Band LSI |
| CXD2932AR-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS Base Band LSI |
| CXD2951GA-2 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single Chip GPS LSI |
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