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參數(shù)資料
| 型號： | CXD3029R |
| 廠商： | Sony Corporation |
| 英文描述： | Silver Mica Capacitor; Capacitance:25000pF; Capacitance Tolerance:+/- 5%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:No RoHS Compliant: No |
| 中文描述： | CD數(shù)字信號處理器，具有內(nèi)置數(shù)字伺服防震內(nèi)存控制器數(shù)字高 |
| 文件頁數(shù)： | 181/201頁 |
| 文件大?。?/td> | 2424K |
| 代理商： | CXD3029R |
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181
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CXD3029R
$3D (preset: $3D 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 SDF6 SDF5 SDF4 SDF3
0
0
0
0
SFID:
SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When the low frequency component of the tracking error signal obtained from the RF amplifier
is attenuated, the low frequency can be amplified and input to the SLD servo filter.
Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the
DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2,
and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to
M00 can be kept uniform by adjusting the K30 value even during the above switching.
TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When signals other than the tracking error signal from the RF amplifier are input to the SE input
pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.
Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the
DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2,
and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to
M18 can be kept uniform by adjusting the K46 value even during the above switching.
See "
§
5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands.
The focus error (FE) and tracking error (TE) can be generated internally.
When 0, the FE and TE signal input mode results. Input each error signal through the FE and
TE pins. (default)
When 1, the FE and TE signal generation mode results and the FE and TE signals are generated
internally.
TLD2 to TLD0: These turn on and off SLD filter correction independently of the TRK filter.
See $38 (TLC0 to TLC2) and Fig. 5-3.
SFSK:
THID:
THSK:
ABEF:
TLC0
0
1
—
0
1
OFF
ON
OFF
OFF
ON
ON
TLD0
VC level correction
TRK filter
SLD filter
: preset,
—
: don't care
TLC1
0
1
—
0
1
OFF
ON
OFF
OFF
ON
ON
TLD1
Tracking zero level correction
TRK filter
SLD filter
TLC2
0
1
—
0
1
OFF
ON
OFF
OFF
ON
ON
TLD2
Traverse center correction
TRK filter
SLD filter
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