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參數(shù)資料
| 型號： | CXD3048R |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo + Shock-proof Memory Controller + Digital High & Bass Boost |
| 中文描述： | CD數(shù)字信號處理器，具有內(nèi)置數(shù)字伺服防震內(nèi)存控制器數(shù)字高 |
| 文件頁數(shù)： | 101/205頁 |
| 文件大?。?/td> | 1481K |
| 代理商： | CXD3048R |
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CXD3048R
[2] Subcode Interface
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK.
The subcode-Q can be read out after checking CRC of the 80 bits in the subcode frame.
The subcode-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR
comes correctly and CRCF is high.
§2-1. P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
§2-2. 80-bit Subcode-Q Readout
Fig. 2-2 shows the peripheral block of the 80-bit subcode-Q register.
First, subcode-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC
check circuit.
96-bit subcode-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC
check) has been loaded.
When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
The retriggerable monostable multivibrator has a time constant from 270 to 400μs. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the serial/parallel register is not loaded into the parallel/serial register.
While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial
register or the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, these registers will not be
rewritten by CRCOK and others.
The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial
register.
For ring control 1, input and output are shorted during peak meter and level meter modes.
For ring control 2, input and output are shorted during peak meter mode.
This is because the register is reset with each readout in level meter mode, and to prevent readout
destruction in peak meter mode.
As a result, the 96-bit clock must be input in peak meter mode.
The absolute time after peak is stored in the memory in peak meter mode as noted in "Description of peak
meter mode" on page 95. See Timing Chart 2-3.
The clock is input from the SQCK pin to perform these operations. The high and low intervals of the clock
should be between 750ns and 120μs.
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相關(guān)代理商/技術(shù)參數(shù) |
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| CXD305-101R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:C-MOS SIGNAL PROCESSOR |
| CXD3057R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built - in RF Amplifier and Digital Servo, Digital High - Bass Boost |
| CXD3059AR | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost |
| CXD3068Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo |
| CXD3141 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ccd-cmosIC資料 |
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