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參數(shù)資料
| 型號： | CXK77910AYM |
| 廠商： | Sony Corporation |
| 英文描述： | 131,072-Word by 9-Bit High-Speed Synchronous Static RAM(131072字 × 9位高速同步靜態(tài)RAM) |
| 中文描述： | 131,072由9位字高速同步靜態(tài)存儲器（131072字× 9位高速同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 187K |
| 代理商： | CXK77910AYM |
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CXK77910ATM/AYM
Pin Description (2)
CLK (Clock, Positive Edge Triggered)
All timing is controlled by the rising or positive edge
of CLK. All synchronous input and output signals are
registered on the positive edge of CLK with set-up and
hold times referenced to that edge. Since only one edge
of CLK is referenced, the duty cycle of CLK is not
critical.
A0 to A16 (Address)
The Address inputs are decoded on-chip to select
one of 131,072 words. The state of the Address inputs
is registered into the Address register on the positive
edge of CLK. The Address inputs must be valid during
every positive edge with all set-up and hold times
referenced to that edge.
I/O0 to I/O8 (Data Input/Output)
I/O terminals are three-state and data input/output
common. The state is defined by the Control block (refer
to the truth table on page 4).
The data inputs for write operation must be valid
during every positive edge of CLK with all set-up and
hold times referenced to that edge. The data outputs
are triggered by the positive edge of CLK and the
contents of the Output-Registers are presented.
WE (Synchronous Write Enable, Active Low)
WE is used to indicate whether a read or write
operation is to be performed. WE is "LOW" to perform a
write operation. WE is registered on every positive edge
of CLK with set-up and hold times referenced to that
edge. The internal timing required to store data into the
memory array is self-timed.
CE (Synchronous Chip Enable, Active Low)
CE is used to select the Synchronous SRAM when
low (or deselect when high). When selected, the
Synchronous SRAM will perform a read or write
operation (refer to the truth table on page 4). The state
of CE is registered on every positive edge of CLK with
set-up and hold times referenced to that edge.
OE (Synchronous Output Enable, Active Low)
OE is used to indicate that a read operation is to be
performed. If the Synchronous SRAM is selected, the
OE is low to perform a read operation (refer to the truth
table on page 4). The state of OE is registered on every
positive edge of CLK with set-up and hold times
referenced to that edge.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXK77910ATM | 131,072-Word by 9-Bit High-Speed Synchronous Static RAM(131072字 × 9位高速同步靜態(tài)RAM) |
| CXK77B1841AGB | 4Mb Late Write LVTTL High Speed Synchronous SRAM (128K x 36Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (128K x 36位)) |
| CXK77B3641AGB | 4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位)) |
| CXK77B1841GB | 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位)) |
| CXK77B3611AGB- | High Speed Bi-CMOS Synchronous Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77910AYM-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
| CXK77920TM-11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
| CXK77920TM-12 | 制造商:Sony Batteries 功能描述: 制造商:Sony Batteries 功能描述:256K X 9 STANDARD SRAM, 6.5 ns, PDSO44 |
| CXK77920TM-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
| CXK77920YM-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
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