參數(shù)資料
型號: CXK77B3641GB
廠商: Sony Corporation
英文描述: 4Mb Late Write LVTTL High Speed Synchronous SRAM (128K x 36Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (128K x 36位))
中文描述: 4Mb的后寫入LVTTL高速同步SRAM(128K的x 36Bit)(4分位,寫延遲,LVTTL高速同步靜態(tài)隨機(jī)存儲器(128K的× 36位))
文件頁數(shù): 19/22頁
文件大小: 200K
代理商: CXK77B3641GB
128Kx36, Sync LW, LVTTL, rev 4.6
19 / 22
August 12, 1998
SONY
CXK77B3641GB
Bypass Register (1 bit)
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides
the minimum length serial path between TDI and TDO.
ID Registers (32 bits)
The ID Register is 32 bits wide and is encoded as follows:
Boundary Scan Register (70 bits)
The Boundary Scan Registers are 70 bits wide and are listed as follows:
K/K, C/C inputs are sampled through one differential stage and internally inverted to generate internal
K/K, C/C signals for scan registers. Place Holder are required for some NC pins to maintain 70 bits Scan
Register for different types of the same family SRAM and for density upgrades. All Place Holder Reg-
isters are connected to V
SS
internally regardless of pin connection externally. TNC register is True No
Connect i.e. not connected internally. TNC register information should be ignored during BSCAN test-
ing.
ID[0}
1
Sony ID
ID[11:1]
0000 1110 001
Part Number
ID[27:12]
0000 0000 0001 1001
Revision Number
ID[31:28]
xxxx
DQ
36
SA
17
SW, SBWx
5
SS, G
2
K, K, C, C
4
ZZ
1
M1, M2
2
Place Holder
2
TNC
1
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