參數(shù)資料
型號(hào): CXP83240A
廠商: Sony Corporation
英文描述: CMOS 8-bit Single Chip Microcomputer
中文描述: 的CMOS 8位單片機(jī)
文件頁(yè)數(shù): 17/24頁(yè)
文件大?。?/td> 557K
代理商: CXP83240A
– 17 –
CXP83232A/83240A
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Note 1)
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FE
H
).
t
sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01", 16000/fc (upper two bits = "11")
Note 2)
The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, V
DD
= 4.5 to 5.5V, Vss = 0V)
Item
CS0
↓ →
SCK0
delay time
CS0
↑ →
SCK0
float delay time
CS0
↓ →
SO0
delay time
CS0
↑ →
SO0
float delay time
CS0 high level width
SCK0 cycle time
SCK0 high and low level
widths
SI0 input setup time
(for SCK0
)
SI0 input hold time
(for SCK0
)
SCK0
↓ →
SO0
delay time
t
DCSK
t
DCSKF
t
DCSO
t
DCSOF
t
WHCS
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
ns
ns
ns
ns
ns
Symbol
Pin
Min.
t
sys + 200
t
sys + 200
t
sys + 200
t
sys + 200
t
sys + 200
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc – 50
100
200
t
sys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
sys + 200
100
Max.
Unit
Conditions
TEX
EC0
EC1
t
EH
t
TH
t
EL
t
TL
t
EF
t
TF
t
ER
t
TR
0.2V
DD
0.8V
DD
Fig. 3. Event count clock timing
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