參數(shù)資料
型號： CXP836P61Q-1-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 14 MM, 0.65 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 16/31頁
文件大?。?/td> 434K
代理商： CXP836P61Q-1-XXX
– 23 –
CXP836P60, CXP836P61
Serial Transfer (CH1)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
1000
8000/fc
400
4000/fc – 50
100
200
100
200
100
ns
tKCY
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK1
tKH
tKL
SCK1
tSIK
SI1
tKSI
SI1
tKSO
SO1
1000
8000/fc
400
4000/fc – 100
100
200
100
250
125
ns
tKCY
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SI1
SO1
Item
SCK cycle time
SCK high and low level
widths
SI input setup time
(for SCK
↑)
SI input hold time
(for SCK
↑)
SCK
↓ → SO delay time
Symbol
Pin
Conditions
Min.
Max.
Unit
Note 1)
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to normal.
Serial Transfer (CH1)
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Item
SCK cycle time
SCK high and low level
widths
SI input setup time
(for SCK
↑)
SI input hold time
(for SCK
↑)
SCK
↓ → SO delay time
Symbol
Pin
Conditions
Min.
Max.
Unit
Note 1)
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to high.
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