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參數(shù)資料
| 型號： | CY2081WAF |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, UUC27 |
| 封裝： | WAFER-27 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 128K |
| 代理商： | CY2081WAF |
CY2081WAF
Document #: 38-07236 Rev. **
Page 3 of 8
Operation
The CY2081WAF is a third-generation family of clock genera-
tors. The part can be configured for either 5V or 3.3V opera-
tion. The internal ROM tables use EPROM technology, allow-
ing full customization of output frequencies. The reference
oscillator has been designed for 10-MHz to 25-MHz crystals,
providing additional flexibility. No external components are re-
quired with this crystal.
Output Configuration
The CY2081WAF has four independent frequency sources on
chip.
These
are
the
reference
oscillator
and
three
Phase-Locked Loops (PLLs). Each PLL has a specific func-
tion. The PLL3 offers the most output frequency divider op-
tions. PLL1 is controlled by the select inputs (S0–S2) to pro-
vide eight user-selectable frequencies with smooth slewing
between frequencies. PLL2 provides the most accurate clock.
It is often used for miscellaneous frequencies not provided by
the other frequency sources.
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the applica-
tion note “Understanding the CY2291, CY2292 and CY2295”
for information on configuring the part.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW. If system shutdown is enabled (the default), a
LOW on this pin also shuts off the PLLs, counters, the refer-
ence oscillator, and all other active components. The resulting
current on the VDD pins will be less than 50 A and is typically
10
A. After leaving shutdown mode, the PLLs will have to
re-lock. All outputs have a weak pull-down so that the outputs
do not float when three-stated.[3]
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combina-
tion. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply forc-
es a three-state condition.[2]
PLL1 can slew (transition) smoothly between 8 MHz and the
maximum output frequency (100 MHz at 5V; 80 MHz at 3.3V).
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