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參數(shù)資料
| 型號(hào)： | CY22388_06 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Factory Programmable Quad PLL Clock Generator with VCXO |
| 中文描述： | 四工廠可編程鎖相環(huán)時(shí)鐘發(fā)生器，石英振蕩器 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 294K |
| 代理商： | CY22388_06 |
CY22388/89/91
Document #: 38-07734 Rev. *B
Page 6 of 10
DC Parameters
[4]
Parameter
I
OH[5]
I
OL[5]
I
IH
I
IL
V
IH
V
IL
V
VCXO
C
IN
I
VDD
C
INXIN
C
INXTAL
Description
Conditions
Min.
12
12
–
–
Typ.
–
–
5
5
–
–
–
–
60
15
12
Max.
–
–
10
10
–
0.3xA
VDD
A
VDD
7
–
–
–
Unit
mA
mA
μA
μA
V
V
V
pF
mA
pF
pF
Output High Current
Output Low Current
Input High Current
Input Low Current
Input High Voltage
Input Low Voltage
VIN Input Range
Input Capacitance
Supply Current
Input Capacitance at XIN VCXO Disabled External Reference
Input Capacitance at
Crystal
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
V
IH
= V
DD
, excluding Vin, Xin
V
IL
= 0V, excluding Vin, Xin
FS0/1/2 OE input CMOS levels
FS0/1/2 OE input CMOS levels
0.7xA
VDD
–
0
–
–
–
–
FS0/1/2 and OE Pins only
V
DD
/AV
DD
/V
DDL
Current
VCXO Disabled Fixed Freq. Oscillator
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
5. Custom Drive level and is available upon request
AC Parameters
Parameter
[4]
1/t1
DC1
Description
Conditions
Min.
4.2
45
Typ. Max. Units
–
166
50
55
Output Frequency
Output Duty Cycle
(excluding REFOUT
PLL
minmax
/Divider
maximum
Duty Cycle is defined in
Figure 4
; t
2
/t
1
, 50% of V
DD
External reference duty cycle between 40% and 60% measured at
V
DD
/2 (Clock output is
125 MHz)
Duty Cycle is defined in
Figure 4
; t
2
/t
1
, 50% of V
DD
External reference duty cycle between 40% and 60% measured at
V
DD
/2 (Clock output is
125 MHz)
Duty Cycle is defined in
Figure 4
; t
2
/t
1
, 50% of V
DD
(XIN Duty Cycle = 45/55%)
Output Clock Edge Rate. Measured from 20% to 80% of
V
DD
. C
LOAD
= 15 pF. See
Figure 5
.
Output Clock Edge Rate. Measured from 80% to 20% of
V
DD
. C
LOAD
= 15pF See
Figure 5
.
Period Jitter
MHz
%
DC2
Output Duty Cycle
40
50
60
%
DC
REFOUT
Output Duty Cycle
40
50
60
%
ER
Rising Edge Rate
0.75
1.2
–
V/ns
EF
Falling Edge Rate
0.75
1.2
–
V/ns
T
9
T
10
f
XO
Clock Jitter
PLL Lock Time
VCXO Crystal Pull
Range
–
–
±250
1
–
5
–
ps
ms
ppm
Usingnon-
SMD-49crystalspecifiedin
“CY22388 Application
Note, ANC0002”
Nominal Crystal Frequency Input assumed (0 ppm)@25°C and 3.3V
Using
SMD-49 crystal specified in
“CY22388 Application
Note, ANC0002”
Nominal Crystal Frequency Input assumed (0 ppm)@25°C and 3.3V
±110 ±120
±105 ±120
–
ppm
[+] Feedback
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