參數(shù)資料
型號: CY22391LFXC-XXX
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Factory Programmable Quad PLL Clock Generator with VCXO
中文描述: 166 MHz, OTHER CLOCK GENERATOR, QCC32
封裝: 5 X 5 MM, LEAD FREE, MO-220, QFN-32
文件頁數(shù): 3/10頁
文件大?。?/td> 294K
代理商: CY22391LFXC-XXX
CY22388/89/91
Document #: 38-07734 Rev. *B
Page 3 of 10
CLKC
frequencies come from the same PLL but can have different
divider values.
In order to minimize PPM (Parts Per Million) error on the clock
outputs, a user should choose a crystal reference frequency
that is a common multiple of the desired PLL frequencies.
While this would be the ideal situation, this is not always the
case and the PLLs have high-resolution counters internally to
help minimize frequency deviation from the desired frequency.
and
CLKE
have
related
frequencies.
Related
PLL VCO frequencies are generated by the following
equation: F
VCO
= F
REF
* (P / Q)
Where F
REF
is the reference input frequency, P is the PLL
feedback divider and Q is the reference input divider.
A PLL is a feedback system where the VCO frequency divided
by P and reference frequency divided by Q are constantly
beingcomparedandtheVCOfrequencyisadjustedto achieve
a locked state.
Figure 1
is a simplified drawing of a PLL.
Figure 1.
Frequency Select Pin Operation
F
R E F
/ Q
V C O
a n d
O t h e r
c o m p o n e n t s
/ P
F
V C O
Table 1. CY22388 16-pin TSSOP
Output Signal
Frequency Selection
Lines
S2S1S0
S1S0
S0
FIXED
CLOCK A
CLOCK B
CLOCK C & CLOCK D
CLOCK E
Table 2. CY22389 20-pin TSSOP
Output Signal
Frequency Selection
Lines
S2S1S0
S1S0
CLOCK A
CLOCK B & CLOCK C
CLOCK D, CLOCK E, & CLOCK F S0
CLOCK G
CLOCK H
FIXED
COPY OF CLOCK D
Table 3. CY22391 32-pin QFN
Output Signal
Frequency Selection
Lines
S2S1S0
S1S0
CLOCK A
CLOCK B & CLOCK C
CLOCK D, CLOCK E, & CLOCK F S0
CLOCK G
CLOCK H
FIXED
COPY OF CLOCK D
[+] Feedback
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相關代理商/技術參數(shù)
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