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參數(shù)資料
| 型號： | CY22800-071A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Universal Programmable Clock Generator (UPCG) |
| 中文描述： | 通用可編程時(shí)鐘發(fā)生器（UPCG） |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 412K |
| 代理商： | CY22800-071A |
CY22800
Document #: 001-07704 Rev. *A
Page 8 of 10
Test Circuit
Figure 2. Test Circuit Diagram
Timing Definitions
Figure 3. Duty Cycle Definition; DC = t2/t1
Figure 4. Rise and Fall Time Definitions
DC Electrical Specifications
Parameter
Name
Description
Min.
Typ.
Max.
Unit
I
OH
I
OL
C
IN1
C
IN2
Output High Current
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
All input pins except XIN and XOUT
12
24
–
mA
Output Low Current
12
24
–
mA
Input Capacitance
–
–
7
pF
Input Capacitance
XIN and XOUT pins for non-VCXO applica-
tions
–
24
–
pF
I
IH
I
IL
f
XO
V
VCXO
V
IH
V
IL
Input High Current
V
IH
= V
DD
V
IL
= 0V
–
5
10
μ
A
μ
A
Input Low Current
–
–
50
VCXO Pullability Range
±150
–
ppm
VCXO Input Range
0
–
V
DD
–
V
Input High Voltage
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
0.7
–
V
DD
V
DD
Input Low Voltage
–
–
0.3
AC
Electrical
Characteristics
(V
DD
= 3.3V
)
Parameter
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in
Figure 3
, 50% of V
DD
Output Clock Rise Time, 20% - 80% of V
DD
Output Clock Fall Time, 80% - 20% of V
DD
45
50
55
%
t
3
t
4
t
10
Rising Edge Slew Rate
0.8
1.4
–
V/ns
Falling Edge Slew Rate
0.8
1.4
–
V/ns
PLL Lock Time
–
–
3
ms
0.1
μ
F
V
DD
CLKout
C
LOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY22800-072A | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Programmable Clock Generator (UPCG) |
| CY22800-073A | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Programmable Clock Generator (UPCG) |
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| CY22800-076A | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Programmable Clock Generator (UPCG) |
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