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參數資料
| 型號： | CY2283PVC-1 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數： | 3/12頁 |
| 文件大?。?/td> | 219K |
| 代理商： | CY2283PVC-1 |
CY2283
PRELIMINARY
3
CPU and PCI Clock Driver Strengths
Matched impedances on both rising and falling edges on
the output drivers
Output impedance: 25
(typical) measured at 1.5V
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to “0”.
I
2
C Address for the CY2283 is:
Actual Clock Frequency Values
Clock Output
Target
Frequency
(MHz)
Actual
Frequency
(MHz)
PPM
CPUCLK
66.67
66.51
–2346
CPUCLK
75.0
75.0
0
CPUCLK
83.33
83.14
-2346
CPUCLK
100.0
99.77
-2346
USBCLK
48.0
48.01
167
Power Management Logic
[4]
- Active when MODE pin is held ‘LOW’
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
PCICLK
PCICLK_F
Other
Clocks
Osc.
PLLs
X
X
0
Low
Low
Stopped
Stopped
Off
Off
0
0
1
Low
Low
Running
Running
Running
Running
0
1
1
Low
33/30 MHz
Running
Running
Running
Running
1
0
1
66/75/83/100MHz
Low
Running
Running
Running
Running
1
1
1
66/75/83/100MHz
30/33.3 MHz
Running
Running
Running
Running
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Pin #
--
Description
(Reserved) drive to ‘0’
Bit 6
--
(Reserved) drive to ‘0’
Bit 5
--
(Reserved) drive to ‘0’
Bit 4
--
(Reserved) drive to ‘0’
Bit 3
--
(Reserved) drive to ‘0’
Bit 2
--
(Reserved) drive to ‘0’
Bit 1
Bit 0
--
Bit 1
1
1
0
0
Bit 0
1 - Three-State
0 - N/A
1 - Testmode
0 - Normal Operation
Select Functions
Functional Description
Three-State
Test Mode
[6]
Outputs
CPU
PCI, PCI_F
Hi-Z
SDRAM
Hi-Z
Ref
IOAPIC
Hi-Z
USBCLK
Hi-Z
AGP
Hi-Z
TCLK/2
[5]
Hi-Z
Hi-Z
TCLK/4
TCLK/2
TCLK
TCLK
TCLK/2
TCLK/2
Notes:
4.
5.
6.
AGP clocks are free-running and stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.
TCLK supplied on the XTALIN pin in Test Mode.
Valid only for SEL1=0.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY2283PVC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs |
| CY2285 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
| CY2285PVC-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| CY2285PVC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
| CY2285PVC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
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