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參數(shù)資料
| 型號： | CY2283PVC-2 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 219K |
| 代理商： | CY2283PVC-2 |
CY2283
PRELIMINARY
7
Switching Characteristics for CY2283-2
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t
1
t
2
All
Output Duty Cycle
t
1
= t
1A
÷
t
1B
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 0.4V and 2.4V, V
DDCPU
= 3.3V
Between 0.4V and 2.4V
TBD
TBD
TBD
%
CPUCLK
CPU Clock Rising and
Falling Edge Rate
TBD
TBD
TBD
V/ns
t
2
SDRAM,
AGP, REF0
SDRAM, AGP, REF0 Clock
Rising and Falling Edge
Rate
TBD
TBD
TBD
V/ns
t
2
PCI
PCI Rising and Falling
Edge Rate
Between 0.4V and 2.4V
TBD
TBD
TBD
V/ns
t
3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 0.4V and 2.4V, V
DDCPU
= 3.3V
Between 2.0V and 0.4V, V
DDCPU
= 2.5V
Between 2.4V and 0.4V, V
DDCPU
= 3.3V
Measured at 1.25V, V
DDCPU
= 2.5V
Measured at 1.5V, V
DDCPU
= 3.3V
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
TBD
TBD
TBD
ns
t
4
CPUCLK
CPU Clock Fall Time
TBD
TBD
TBD
ns
t
5
CPUCLK
CPU-CPU Clock Skew
TBD
TBD
TBD
ps
t
6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
TBD
TBD
TBD
ns
t
7
CPUCLK,
SDRAM
CPU-SDRAM Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
TBD
TBD
TBD
ps
t
8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
TBD
TBD
TBD
ps
t
9
PCICLK,
AGP
PCI-AGP Clock Skew
Measured at 1.5V
TBD
TBD
TBD
ps
t
10
CPUCLK,
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
TBD
TBD
TBD
ps
t
10
t
10
t
11
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
TBD
TBD
TBD
ps
AGP
Cycle-Cycle Clock Jitter
Measured at 1.5V
TBD
TBD
TBD
ps
CPUCLK,
PCICLK,
AGP,SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock sta-
bilization from power-up
TBD
TBD
TBD
ms
Timing Requirement for the I
2
C Bus
Parameter
t
12
t
13
t
14
t
15
t
16
t
17
t
18
Description
Min.
0
Max.
100
Unit
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
SCLK Clock Frequency
Time the bus must be free before a new transmission can start
4.7
Hold time start condition. After this period the first clock pulse is generated.
4
The LOW period of the clock
4.7
The HIGH period of the clock
4
Set-up time for start condition. (Only relevant for a repeated start condition.)
4.7
Hold time DATA
for CBUS compatible masters
for I
2
C devices
5
0
t
19
t
20
t
21
t
22
DATA input set-up time
250
ns
μ
s
ns
μ
s
Rise time of both SDATA and SCLK inputs
1
Fall time of both SDATA and SCLK inputs
300
Set-up time for stop condition
4.0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2285 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
| CY2285PVC-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| CY2285PVC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
| CY2285PVC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
| CY2287 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Spread Spectrum Clock Synthesizer/Driver with USB, Hublink, and SDRAM Support |
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