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參數(shù)資料
| 型號(hào)： | CY23EP09 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer(2.5V或3.3V,10-220 MHz,低抖動(dòng), 9輸出零延遲緩沖器) |
| 中文描述： | 2.5V或3.3V，10-220兆赫，低抖動(dòng)，9輸出零延遲緩沖器電壓（2.5V或3.3V的,10 - 220頻率，低抖動(dòng)，9輸出零延遲緩沖器） |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 359K |
| 代理商： | CY23EP09 |
CY23EP09
Document #: 38-07760 Rev. *B
Page 2 of 13
Pin Definition
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load
of 5 pF plus any additional load externally connected to this
pin. For applications requiring zero input-output delay, the total
load on each output pin (including CLKOUT) must be the
same. If input-output delay adjustments are required, the
CLKOUT load may be changed to vary the delay between the
REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled “CY2305 and CY2309 as PCI and SDRAM Buffers”.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal
Description
REF
[1]
CLKA1
[2]
CLKA2
[2]
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
[2]
CLKB4
[2]
GND
V
DD
CLKA3
[2]
CLKA4
[2]
CLKOUT
[2]
Input reference frequency
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V or 2.5V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3V or 2.5V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
[4]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
相關(guān)PDF資料 |
PDF描述 |
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| CY23FP12OXIT | 200-MHz Field Programmable Zero Delay Buffer |
| CY23FP12OC | Coaxial Cable; Coaxial RG/U Type:59; Impedance:75ohm; Conductor Size AWG:20; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Capacitance:16.2pF/ft; Conductor Material:Steel; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CY23FP12OCT | Belden RG-59/U Coaxial Cable, Wire Size: 20 AWG, Color: Black, Length: 1000 feet, Conductor Material: Bare Copper, Shielding: 40 % Aluminum Braid, Jacket: PVC |
| CY23FP12OI | Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Conductor Material:Copper; Jacket Color:Black; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CY23FP12OIT | Coaxial Cable; Coaxial RG/U Type:11; Impedance:75ohm; Conductor Size AWG:14; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Conductor Material:Copper; Jacket Color:Black; Leaded Process Compatible:Yes RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23EP09_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer |
| CY23EP09SXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY23EP09SXC-1 | 功能描述:鎖相環(huán) - PLL 3.3VZDB COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23EP09SXC-1H | 功能描述:鎖相環(huán) - PLL 2.5V 3.3V 10-220 MHz Zero Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23EP09SXC-1HT | 功能描述:鎖相環(huán) - PLL 3.3VZDB COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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